Commit 4519c2bf authored by Paul Walmsley's avatar Paul Walmsley Committed by paul

OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz

According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the
DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC
clock frequency from 83MHz to 166MHz.  CDP code unconditionally
unlocked the DLL whenever shifting to a lower SDRC speed, but this
seems unnecessary and error-prone, as the DLL is no longer able to
compensate for process, voltage, and temperature variations.  Instead,
only unlock the DLL when the SDRC clock rate would be less than 83MHz.
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent b2abb271
...@@ -281,6 +281,8 @@ static struct omap_clk omap34xx_clks[] = { ...@@ -281,6 +281,8 @@ static struct omap_clk omap34xx_clks[] = {
#define MAX_DPLL_WAIT_TRIES 1000000 #define MAX_DPLL_WAIT_TRIES 1000000
#define MIN_SDRC_DLL_LOCK_FREQ 83000000
/** /**
* omap3_dpll_recalc - recalculate DPLL rate * omap3_dpll_recalc - recalculate DPLL rate
* @clk: DPLL struct clk * @clk: DPLL struct clk
...@@ -703,6 +705,7 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) ...@@ -703,6 +705,7 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
{ {
u32 new_div = 0; u32 new_div = 0;
u32 unlock_dll = 0;
unsigned long validrate, sdrcrate; unsigned long validrate, sdrcrate;
struct omap_sdrc_params *sp; struct omap_sdrc_params *sp;
...@@ -729,6 +732,11 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) ...@@ -729,6 +732,11 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
if (!sp) if (!sp)
return -EINVAL; return -EINVAL;
if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
pr_debug("clock: will unlock SDRC DLL\n");
unlock_dll = 1;
}
pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
validrate); validrate);
pr_info("clock: SDRC timing params used: %08x %08x %08x\n", pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
...@@ -739,7 +747,7 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) ...@@ -739,7 +747,7 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
/* REVISIT: Add SDRC_MR changing to this code also */ /* REVISIT: Add SDRC_MR changing to this code also */
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
sp->actim_ctrlb, new_div); sp->actim_ctrlb, new_div, unlock_dll);
return 0; return 0;
} }
......
...@@ -40,22 +40,23 @@ ...@@ -40,22 +40,23 @@
/* /*
* Change frequency of core dpll * Change frequency of core dpll
* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
* r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
* SDRC rates < 83MHz
*/ */
ENTRY(omap3_sram_configure_core_dpll) ENTRY(omap3_sram_configure_core_dpll)
stmfd sp!, {r1-r12, lr} @ store regs to stack stmfd sp!, {r1-r12, lr} @ store regs to stack
ldr r4, [sp, #52] @ pull extra args off the stack
dsb @ flush buffered writes to interconnect dsb @ flush buffered writes to interconnect
cmp r3, #0x2 cmp r3, #0x2
blne configure_sdrc blne configure_sdrc
cmp r3, #0x2 cmp r4, #0x1
bleq unlock_dll
blne lock_dll blne lock_dll
cmp r3, #0x1
blne unlock_dll
bl sdram_in_selfrefresh @ put the SDRAM in self refresh bl sdram_in_selfrefresh @ put the SDRAM in self refresh
bl configure_core_dpll bl configure_core_dpll
bl enable_sdrc bl enable_sdrc
cmp r3, #0x1 cmp r4, #0x1
blne wait_dll_unlock bleq wait_dll_unlock
cmp r3, #0x2
blne wait_dll_lock blne wait_dll_lock
cmp r3, #0x1 cmp r3, #0x1
blne configure_sdrc blne configure_sdrc
......
...@@ -23,7 +23,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); ...@@ -23,7 +23,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2); u32 sdrc_actim_ctrlb, u32 m2,
u32 unlock_dll);
/* Do not use these */ /* Do not use these */
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
...@@ -60,7 +61,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz; ...@@ -60,7 +61,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2); u32 sdrc_actim_ctrlb, u32 m2,
u32 unlock_dll);
extern unsigned long omap3_sram_configure_core_dpll_sz; extern unsigned long omap3_sram_configure_core_dpll_sz;
#endif #endif
...@@ -365,16 +365,17 @@ static inline int omap243x_sram_init(void) ...@@ -365,16 +365,17 @@ static inline int omap243x_sram_init(void)
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 sdrc_actim_ctrlb,
u32 m2); u32 m2, u32 unlock_dll);
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2) u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
{ {
if (!_omap3_sram_configure_core_dpll) if (!_omap3_sram_configure_core_dpll)
omap_sram_error(); omap_sram_error();
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
sdrc_actim_ctrla, sdrc_actim_ctrla,
sdrc_actim_ctrlb, m2); sdrc_actim_ctrlb, m2,
unlock_dll);
} }
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment