Commit 456bf0f6 authored by Leo Yan's avatar Leo Yan Committed by Ben Hutchings

clk: hisilicon: fix lock assignment

commit 55da97e3 upstream.

In clock driver initialize phase the spinlock is missed to assignment
to struct clkgate_separated, finally there have no locking to protect
exclusive accessing for clock registers.

This bug introduces the console has no output after enable coresight
driver on 96boards Hikey; this is because console using UART3, which
has shared the same register with coresight clock enabling bit. After
applied this patch it can assign lock properly to protect exclusive
accessing, and console can work well after enabled coresight modules.

Fixes: 0aa0c95f ("clk: hisilicon: add common clock support")
Signed-off-by: default avatarLeo Yan <leo.yan@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarBen Hutchings <ben@decadent.org.uk>
parent 646fe8e6
...@@ -122,6 +122,7 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, ...@@ -122,6 +122,7 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name,
sclk->bit_idx = bit_idx; sclk->bit_idx = bit_idx;
sclk->flags = clk_gate_flags; sclk->flags = clk_gate_flags;
sclk->hw.init = &init; sclk->hw.init = &init;
sclk->lock = lock;
clk = clk_register(dev, &sclk->hw); clk = clk_register(dev, &sclk->hw);
if (IS_ERR(clk)) if (IS_ERR(clk))
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment