Commit 4600522a authored by Ben Skeggs's avatar Ben Skeggs

drm/nvd0/disp: start on interrupt handling

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 51beb428
...@@ -100,6 +100,44 @@ evo_kick(u32 *push, struct drm_device *dev, int id) ...@@ -100,6 +100,44 @@ evo_kick(u32 *push, struct drm_device *dev, int id)
/****************************************************************************** /******************************************************************************
* IRQ * IRQ
*****************************************************************************/ *****************************************************************************/
static void
nvd0_display_intr(struct drm_device *dev)
{
u32 intr = nv_rd32(dev, 0x610088);
if (intr & 0x00000002) {
u32 stat = nv_rd32(dev, 0x61009c);
int chid = ffs(stat) - 1;
if (chid >= 0) {
u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12));
u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12));
u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12));
NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x "
"0x%08x 0x%08x\n",
chid, (mthd & 0x0000ffc), data, mthd, unkn);
nv_wr32(dev, 0x61009c, (1 << chid));
nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000);
}
intr &= ~0x00000002;
}
if (intr & 0x01000000) {
u32 stat = nv_rd32(dev, 0x6100bc);
nv_wr32(dev, 0x6100bc, stat);
intr &= ~0x01000000;
}
if (intr & 0x02000000) {
u32 stat = nv_rd32(dev, 0x6108bc);
nv_wr32(dev, 0x6108bc, stat);
intr &= ~0x02000000;
}
if (intr)
NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr);
}
/****************************************************************************** /******************************************************************************
* Init * Init
...@@ -190,6 +228,7 @@ nvd0_display_destroy(struct drm_device *dev) ...@@ -190,6 +228,7 @@ nvd0_display_destroy(struct drm_device *dev)
pci_free_consistent(pdev, PAGE_SIZE, disp->evo[0].ptr, disp->evo[0].handle); pci_free_consistent(pdev, PAGE_SIZE, disp->evo[0].ptr, disp->evo[0].handle);
nouveau_gpuobj_ref(NULL, &disp->mem); nouveau_gpuobj_ref(NULL, &disp->mem);
nouveau_irq_unregister(dev, 26);
dev_priv->engine.display.priv = NULL; dev_priv->engine.display.priv = NULL;
kfree(disp); kfree(disp);
...@@ -208,6 +247,9 @@ nvd0_display_create(struct drm_device *dev) ...@@ -208,6 +247,9 @@ nvd0_display_create(struct drm_device *dev)
return -ENOMEM; return -ENOMEM;
dev_priv->engine.display.priv = disp; dev_priv->engine.display.priv = disp;
/* setup interrupt handling */
nouveau_irq_register(dev, 26, nvd0_display_intr);
/* hash table and dma objects for the memory areas we care about */ /* hash table and dma objects for the memory areas we care about */
ret = nouveau_gpuobj_new(dev, NULL, 4 * 1024, 0x1000, 0, &disp->mem); ret = nouveau_gpuobj_new(dev, NULL, 4 * 1024, 0x1000, 0, &disp->mem);
if (ret) if (ret)
......
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