Commit 47e45faf authored by Philippe Schenker's avatar Philippe Schenker Committed by Shawn Guo

ARM: dts: imx6ull-colibri: Add sleep mode to fec

Do not change the clock as the power for this phy is switched
with that clock.
Signed-off-by: default avatarPhilippe Schenker <philippe.schenker@toradex.com>
Acked-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: default avatarOleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent ab2b870a
......@@ -62,8 +62,9 @@ &ecspi1 {
};
&fec2 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet2>;
pinctrl-1 = <&pinctrl_enet2_sleep>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
......@@ -220,6 +221,21 @@ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
>;
};
pinctrl_enet2_sleep: enet2sleepgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0
MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0
MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0
MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0
>;
};
pinctrl_ecspi1_cs: ecspi1-cs-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
......
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