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Commit 48f36de9 authored by Dinh Nguyen's avatar Dinh Nguyen
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arm64: dts: agilex: populate clock dts entries for Intel SoCFPGA Agilex 

Add clock dts entries to the Intel SoCFPGA Agilex platform.
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent b3a9e3b9
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arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View file @ 48f36de9
...@@ -6,6 +6,7 @@ ...@@ -6,6 +6,7 @@
/dts-v1/; /dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h> #include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/agilex-clock.h>
/ { / {
compatible = "intel,socfpga-agilex"; compatible = "intel,socfpga-agilex";
...@@ -101,6 +102,40 @@ base_fpga_region { ...@@ -101,6 +102,40 @@ base_fpga_region {
fpga-mgr = <&fpga_mgr>; fpga-mgr = <&fpga_mgr>;
}; };
clkmgr: clock-controller@ffd10000 {
compatible = "intel,agilex-clkmgr";
reg = <0xffd10000 0x1000>;
#clock-cells = <1>;
};
clocks {
cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
cb_intosc_ls_clk: cb-intosc-ls-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
f2s_free_clk: f2s-free-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
};
qspi_clk: qspi-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
};
gmac0: ethernet@ff800000 { gmac0: ethernet@ff800000 {
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff800000 0x2000>; reg = <0xff800000 0x2000>;
...@@ -114,6 +149,8 @@ gmac0: ethernet@ff800000 { ...@@ -114,6 +149,8 @@ gmac0: ethernet@ff800000 {
snps,multicast-filter-bins = <256>; snps,multicast-filter-bins = <256>;
iommus = <&smmu 1>; iommus = <&smmu 1>;
altr,sysmgr-syscon = <&sysmgr 0x44 0>; altr,sysmgr-syscon = <&sysmgr 0x44 0>;
clocks = <&clkmgr AGILEX_EMAC0_CLK>;
clock-names = "stmmaceth";
status = "disabled"; status = "disabled";
}; };
...@@ -130,6 +167,8 @@ gmac1: ethernet@ff802000 { ...@@ -130,6 +167,8 @@ gmac1: ethernet@ff802000 {
snps,multicast-filter-bins = <256>; snps,multicast-filter-bins = <256>;
iommus = <&smmu 2>; iommus = <&smmu 2>;
altr,sysmgr-syscon = <&sysmgr 0x48 8>; altr,sysmgr-syscon = <&sysmgr 0x48 8>;
clocks = <&clkmgr AGILEX_EMAC1_CLK>;
clock-names = "stmmaceth";
status = "disabled"; status = "disabled";
}; };
...@@ -146,6 +185,8 @@ gmac2: ethernet@ff804000 { ...@@ -146,6 +185,8 @@ gmac2: ethernet@ff804000 {
snps,multicast-filter-bins = <256>; snps,multicast-filter-bins = <256>;
iommus = <&smmu 3>; iommus = <&smmu 3>;
altr,sysmgr-syscon = <&sysmgr 0x4c 16>; altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
clocks = <&clkmgr AGILEX_EMAC2_CLK>;
clock-names = "stmmaceth";
status = "disabled"; status = "disabled";
}; };
...@@ -196,6 +237,7 @@ i2c0: i2c@ffc02800 { ...@@ -196,6 +237,7 @@ i2c0: i2c@ffc02800 {
reg = <0xffc02800 0x100>; reg = <0xffc02800 0x100>;
interrupts = <0 103 4>; interrupts = <0 103 4>;
resets = <&rst I2C0_RESET>; resets = <&rst I2C0_RESET>;
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -206,6 +248,7 @@ i2c1: i2c@ffc02900 { ...@@ -206,6 +248,7 @@ i2c1: i2c@ffc02900 {
reg = <0xffc02900 0x100>; reg = <0xffc02900 0x100>;
interrupts = <0 104 4>; interrupts = <0 104 4>;
resets = <&rst I2C1_RESET>; resets = <&rst I2C1_RESET>;
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -216,6 +259,7 @@ i2c2: i2c@ffc02a00 { ...@@ -216,6 +259,7 @@ i2c2: i2c@ffc02a00 {
reg = <0xffc02a00 0x100>; reg = <0xffc02a00 0x100>;
interrupts = <0 105 4>; interrupts = <0 105 4>;
resets = <&rst I2C2_RESET>; resets = <&rst I2C2_RESET>;
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -226,6 +270,7 @@ i2c3: i2c@ffc02b00 { ...@@ -226,6 +270,7 @@ i2c3: i2c@ffc02b00 {
reg = <0xffc02b00 0x100>; reg = <0xffc02b00 0x100>;
interrupts = <0 106 4>; interrupts = <0 106 4>;
resets = <&rst I2C3_RESET>; resets = <&rst I2C3_RESET>;
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -236,6 +281,7 @@ i2c4: i2c@ffc02c00 { ...@@ -236,6 +281,7 @@ i2c4: i2c@ffc02c00 {
reg = <0xffc02c00 0x100>; reg = <0xffc02c00 0x100>;
interrupts = <0 107 4>; interrupts = <0 107 4>;
resets = <&rst I2C4_RESET>; resets = <&rst I2C4_RESET>;
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -248,6 +294,9 @@ mmc: dwmmc0@ff808000 { ...@@ -248,6 +294,9 @@ mmc: dwmmc0@ff808000 {
fifo-depth = <0x400>; fifo-depth = <0x400>;
resets = <&rst SDMMC_RESET>; resets = <&rst SDMMC_RESET>;
reset-names = "reset"; reset-names = "reset";
clocks = <&clkmgr AGILEX_L4_MP_CLK>,
<&clkmgr AGILEX_SDMMC_CLK>;
clock-names = "biu", "ciu";
iommus = <&smmu 5>; iommus = <&smmu 5>;
status = "disabled"; status = "disabled";
}; };
...@@ -286,6 +335,8 @@ pdma: pdma@ffda0000 { ...@@ -286,6 +335,8 @@ pdma: pdma@ffda0000 {
#dma-requests = <32>; #dma-requests = <32>;
resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
reset-names = "dma", "dma-ocp"; reset-names = "dma", "dma-ocp";
clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
clock-names = "apb_pclk";
}; };
rst: rstmgr@ffd11000 { rst: rstmgr@ffd11000 {
...@@ -312,6 +363,9 @@ smmu: iommu@fa000000 { ...@@ -312,6 +363,9 @@ smmu: iommu@fa000000 {
<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
stream-match-mask = <0x7ff0>; stream-match-mask = <0x7ff0>;
clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
<&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
<&clkmgr AGILEX_L4_MAIN_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -324,6 +378,7 @@ spi0: spi@ffda4000 { ...@@ -324,6 +378,7 @@ spi0: spi@ffda4000 {
resets = <&rst SPIM0_RESET>; resets = <&rst SPIM0_RESET>;
reg-io-width = <4>; reg-io-width = <4>;
num-cs = <4>; num-cs = <4>;
clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -336,6 +391,7 @@ spi1: spi@ffda5000 { ...@@ -336,6 +391,7 @@ spi1: spi@ffda5000 {
resets = <&rst SPIM1_RESET>; resets = <&rst SPIM1_RESET>;
reg-io-width = <4>; reg-io-width = <4>;
num-cs = <4>; num-cs = <4>;
clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -357,24 +413,32 @@ timer0: timer0@ffc03000 { ...@@ -357,24 +413,32 @@ timer0: timer0@ffc03000 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
interrupts = <0 113 4>; interrupts = <0 113 4>;
reg = <0xffc03000 0x100>; reg = <0xffc03000 0x100>;
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
clock-names = "timer";
}; };
timer1: timer1@ffc03100 { timer1: timer1@ffc03100 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
interrupts = <0 114 4>; interrupts = <0 114 4>;
reg = <0xffc03100 0x100>; reg = <0xffc03100 0x100>;
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
clock-names = "timer";
}; };
timer2: timer2@ffd00000 { timer2: timer2@ffd00000 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
interrupts = <0 115 4>; interrupts = <0 115 4>;
reg = <0xffd00000 0x100>; reg = <0xffd00000 0x100>;
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
clock-names = "timer";
}; };
timer3: timer3@ffd00100 { timer3: timer3@ffd00100 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
interrupts = <0 116 4>; interrupts = <0 116 4>;
reg = <0xffd00100 0x100>; reg = <0xffd00100 0x100>;
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
clock-names = "timer";
}; };
uart0: serial0@ffc02000 { uart0: serial0@ffc02000 {
...@@ -385,6 +449,7 @@ uart0: serial0@ffc02000 { ...@@ -385,6 +449,7 @@ uart0: serial0@ffc02000 {
reg-io-width = <4>; reg-io-width = <4>;
resets = <&rst UART0_RESET>; resets = <&rst UART0_RESET>;
status = "disabled"; status = "disabled";
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
}; };
uart1: serial1@ffc02100 { uart1: serial1@ffc02100 {
...@@ -394,6 +459,7 @@ uart1: serial1@ffc02100 { ...@@ -394,6 +459,7 @@ uart1: serial1@ffc02100 {
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
resets = <&rst UART1_RESET>; resets = <&rst UART1_RESET>;
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -411,6 +477,7 @@ usb0: usb@ffb00000 { ...@@ -411,6 +477,7 @@ usb0: usb@ffb00000 {
phy-names = "usb2-phy"; phy-names = "usb2-phy";
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc"; reset-names = "dwc2", "dwc2-ecc";
clocks = <&clkmgr AGILEX_USB_CLK>;
iommus = <&smmu 6>; iommus = <&smmu 6>;
status = "disabled"; status = "disabled";
}; };
...@@ -424,6 +491,7 @@ usb1: usb@ffb40000 { ...@@ -424,6 +491,7 @@ usb1: usb@ffb40000 {
resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc"; reset-names = "dwc2", "dwc2-ecc";
iommus = <&smmu 7>; iommus = <&smmu 7>;
clocks = <&clkmgr AGILEX_USB_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -432,6 +500,7 @@ watchdog0: watchdog@ffd00200 { ...@@ -432,6 +500,7 @@ watchdog0: watchdog@ffd00200 {
reg = <0xffd00200 0x100>; reg = <0xffd00200 0x100>;
interrupts = <0 117 4>; interrupts = <0 117 4>;
resets = <&rst WATCHDOG0_RESET>; resets = <&rst WATCHDOG0_RESET>;
clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -440,6 +509,7 @@ watchdog1: watchdog@ffd00300 { ...@@ -440,6 +509,7 @@ watchdog1: watchdog@ffd00300 {
reg = <0xffd00300 0x100>; reg = <0xffd00300 0x100>;
interrupts = <0 118 4>; interrupts = <0 118 4>;
resets = <&rst WATCHDOG1_RESET>; resets = <&rst WATCHDOG1_RESET>;
clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -448,6 +518,7 @@ watchdog2: watchdog@ffd00400 { ...@@ -448,6 +518,7 @@ watchdog2: watchdog@ffd00400 {
reg = <0xffd00400 0x100>; reg = <0xffd00400 0x100>;
interrupts = <0 125 4>; interrupts = <0 125 4>;
resets = <&rst WATCHDOG2_RESET>; resets = <&rst WATCHDOG2_RESET>;
clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -456,6 +527,7 @@ watchdog3: watchdog@ffd00500 { ...@@ -456,6 +527,7 @@ watchdog3: watchdog@ffd00500 {
reg = <0xffd00500 0x100>; reg = <0xffd00500 0x100>;
interrupts = <0 126 4>; interrupts = <0 126 4>;
resets = <&rst WATCHDOG3_RESET>; resets = <&rst WATCHDOG3_RESET>;
clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
status = "disabled"; status = "disabled";
}; };
...@@ -533,6 +605,7 @@ qspi: spi@ff8d2000 { ...@@ -533,6 +605,7 @@ qspi: spi@ff8d2000 {
cdns,fifo-depth = <128>; cdns,fifo-depth = <128>;
cdns,fifo-width = <4>; cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>; cdns,trigger-address = <0x00000000>;
clocks = <&qspi_clk>;
status = "disabled"; status = "disabled";
}; };
......
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
View file @ 48f36de9
...@@ -41,6 +41,14 @@ memory { ...@@ -41,6 +41,14 @@ memory {
/* We expect the bootloader to fill in the reg */ /* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>; reg = <0 0 0 0>;
}; };
soc {
clocks {
osc1 {
clock-frequency = <25000000>;
};
};
};
}; };
&gpio1 { &gpio1 {
......
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