Commit 4948293f authored by Igor Russkikh's avatar Igor Russkikh Committed by David S. Miller

net: aquantia: Introduce new AQC devices and capabilities

A number of new AQC devices is going to be released. To support more
flexible capabilities management a number of static caps instances is now
declared. Devices now are mainly differs by supported speeds, but in future
more parameters will be customized. A set of AQC100 devices have
fibre media, not twisted pair - this is also reflected in
new capabilities definitions.

HW level also now directly exports hw_ops for each of A0/B0 hardware.

PCI configuration now uses a device configuration table where each
device ID is explicitly mapped with hardware OPs and capabilities
structures.
Signed-off-by: default avatarIgor Russkikh <igor.russkikh@aquantia.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent efe779b7
......@@ -46,6 +46,10 @@
#define HW_ATL_NIC_NAME "aQuantia AQtion 10Gbit Network Adapter"
#define AQ_HWREV_ANY 0
#define AQ_HWREV_1 1
#define AQ_HWREV_2 2
#define AQ_NIC_RATE_10G BIT(0)
#define AQ_NIC_RATE_5G BIT(1)
#define AQ_NIC_RATE_5GSR BIT(2)
......
......@@ -23,6 +23,7 @@ struct aq_hw_caps_s {
u64 hw_features;
u64 link_speed_msk;
unsigned int hw_priv_flags;
u32 media_type;
u32 rxds;
u32 txds;
u32 txhwb_alignment;
......@@ -95,6 +96,9 @@ struct aq_stats_s {
#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \
AQ_NIC_LINK_DOWN)
#define AQ_HW_MEDIA_TYPE_TP 1U
#define AQ_HW_MEDIA_TYPE_FIBRE 2U
struct aq_hw_s {
atomic_t flags;
struct aq_nic_cfg_s *aq_nic_cfg;
......@@ -128,11 +132,6 @@ struct aq_hw_ops {
void (*destroy)(struct aq_hw_s *self);
int (*get_hw_caps)(struct aq_hw_s *self,
struct aq_hw_caps_s *aq_hw_caps,
unsigned short device,
unsigned short subsystem_device);
int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
unsigned int frags);
......
......@@ -208,7 +208,8 @@ static void aq_nic_polling_timer_cb(struct timer_list *t)
struct aq_nic_s *aq_nic_alloc_cold(struct pci_dev *pdev,
struct aq_pci_func_s *aq_pci_func,
unsigned int port,
const struct aq_hw_ops *aq_hw_ops)
const struct aq_hw_ops *aq_hw_ops,
const struct aq_hw_caps_s *aq_hw_caps)
{
struct net_device *ndev = NULL;
struct aq_nic_s *self = NULL;
......@@ -230,16 +231,12 @@ struct aq_nic_s *aq_nic_alloc_cold(struct pci_dev *pdev,
self->aq_pci_func = aq_pci_func;
self->aq_hw_ops = *aq_hw_ops;
self->aq_hw_caps = *aq_hw_caps;
self->port = (u8)port;
self->aq_hw = self->aq_hw_ops.create(aq_pci_func, self->port);
self->aq_hw->aq_nic_cfg = &self->aq_nic_cfg;
err = self->aq_hw_ops.get_hw_caps(self->aq_hw, &self->aq_hw_caps,
pdev->device, pdev->subsystem_device);
if (err < 0)
goto err_exit;
aq_nic_cfg_init_defaults(self);
err_exit:
......
......@@ -92,7 +92,8 @@ static inline struct device *aq_nic_get_dev(struct aq_nic_s *self)
struct aq_nic_s *aq_nic_alloc_cold(struct pci_dev *pdev,
struct aq_pci_func_s *aq_pci_func,
unsigned int port,
const struct aq_hw_ops *aq_hw_ops);
const struct aq_hw_ops *aq_hw_ops,
const struct aq_hw_caps_s *aq_hw_caps);
int aq_nic_ndev_init(struct aq_nic_s *self);
struct aq_nic_s *aq_nic_alloc_hot(struct net_device *ndev);
void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx,
......
......@@ -60,20 +60,66 @@ static const struct pci_device_id aq_pci_tbl[] = {
{}
};
const struct aq_board_revision_s hw_atl_boards[] = {
{ AQ_DEVICE_ID_0001, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc107, },
{ AQ_DEVICE_ID_D100, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc100, },
{ AQ_DEVICE_ID_D107, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc107, },
{ AQ_DEVICE_ID_D108, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc108, },
{ AQ_DEVICE_ID_D109, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc109, },
{ AQ_DEVICE_ID_0001, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc107, },
{ AQ_DEVICE_ID_D100, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc100, },
{ AQ_DEVICE_ID_D107, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc107, },
{ AQ_DEVICE_ID_D108, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc108, },
{ AQ_DEVICE_ID_D109, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc109, },
{ AQ_DEVICE_ID_AQC100, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107, },
{ AQ_DEVICE_ID_AQC107, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107, },
{ AQ_DEVICE_ID_AQC108, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc108, },
{ AQ_DEVICE_ID_AQC109, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc109, },
{ AQ_DEVICE_ID_AQC111, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111, },
{ AQ_DEVICE_ID_AQC112, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112, },
{ AQ_DEVICE_ID_AQC100S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc100s, },
{ AQ_DEVICE_ID_AQC107S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107s, },
{ AQ_DEVICE_ID_AQC108S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc108s, },
{ AQ_DEVICE_ID_AQC109S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc109s, },
{ AQ_DEVICE_ID_AQC111S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111s, },
{ AQ_DEVICE_ID_AQC112S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112s, },
{ AQ_DEVICE_ID_AQC111E, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111e, },
{ AQ_DEVICE_ID_AQC112E, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112e, },
};
MODULE_DEVICE_TABLE(pci, aq_pci_tbl);
static const struct aq_hw_ops *aq_pci_probe_get_hw_ops_by_id(struct pci_dev *pdev)
static int aq_pci_probe_get_hw_by_id(struct pci_dev *pdev,
const struct aq_hw_ops **ops,
const struct aq_hw_caps_s **caps)
{
const struct aq_hw_ops *ops = NULL;
int i = 0;
if (pdev->vendor != PCI_VENDOR_ID_AQUANTIA)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(hw_atl_boards); i++) {
if (hw_atl_boards[i].devid == pdev->device &&
(hw_atl_boards[i].revision == AQ_HWREV_ANY ||
hw_atl_boards[i].revision == pdev->revision)) {
*ops = hw_atl_boards[i].ops;
*caps = hw_atl_boards[i].caps;
break;
}
}
ops = hw_atl_a0_get_ops_by_id(pdev);
if (!ops)
ops = hw_atl_b0_get_ops_by_id(pdev);
if (i == ARRAY_SIZE(hw_atl_boards))
return -EINVAL;
return ops;
return 0;
}
struct aq_pci_func_s *aq_pci_func_alloc(const struct aq_hw_ops *aq_hw_ops,
const struct aq_hw_caps_s *aq_hw_caps,
struct pci_dev *pdev)
{
struct aq_pci_func_s *self = NULL;
......@@ -92,17 +138,14 @@ struct aq_pci_func_s *aq_pci_func_alloc(const struct aq_hw_ops *aq_hw_ops,
pci_set_drvdata(pdev, self);
self->pdev = pdev;
err = aq_hw_ops->get_hw_caps(NULL, &self->aq_hw_caps, pdev->device,
pdev->subsystem_device);
if (err < 0)
goto err_exit;
self->aq_hw_caps = *aq_hw_caps;
self->ports = self->aq_hw_caps.ports;
for (port = 0; port < self->ports; ++port) {
struct aq_nic_s *aq_nic = aq_nic_alloc_cold(pdev, self,
port, aq_hw_ops);
port, aq_hw_ops,
aq_hw_caps);
if (!aq_nic) {
err = -ENOMEM;
......@@ -343,14 +386,17 @@ static int aq_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *pci_id)
{
const struct aq_hw_ops *aq_hw_ops = NULL;
const struct aq_hw_caps_s *aq_hw_caps = NULL;
struct aq_pci_func_s *aq_pci_func = NULL;
int err = 0;
err = pci_enable_device(pdev);
if (err < 0)
goto err_exit;
aq_hw_ops = aq_pci_probe_get_hw_ops_by_id(pdev);
aq_pci_func = aq_pci_func_alloc(aq_hw_ops, pdev);
err = aq_pci_probe_get_hw_by_id(pdev, &aq_hw_ops, &aq_hw_caps);
if (err < 0)
goto err_exit;
aq_pci_func = aq_pci_func_alloc(aq_hw_ops, aq_hw_caps, pdev);
if (!aq_pci_func) {
err = -ENOMEM;
goto err_exit;
......
......@@ -15,8 +15,13 @@
#include "aq_common.h"
#include "aq_nic.h"
struct aq_pci_func_s *aq_pci_func_alloc(const struct aq_hw_ops *hw_ops,
struct pci_dev *pdev);
struct aq_board_revision_s {
unsigned short devid;
unsigned short revision;
const struct aq_hw_ops *ops;
const struct aq_hw_caps_s *caps;
};
int aq_pci_func_init(struct aq_pci_func_s *self);
int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i,
char *name, void *aq_vec,
......
......@@ -18,23 +18,67 @@
#include "hw_atl_llh.h"
#include "hw_atl_a0_internal.h"
static int hw_atl_a0_get_hw_caps(struct aq_hw_s *self,
struct aq_hw_caps_s *aq_hw_caps,
unsigned short device,
unsigned short subsystem_device)
{
memcpy(aq_hw_caps, &hw_atl_a0_hw_caps_, sizeof(*aq_hw_caps));
#define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \
.is_64_dma = true, \
.msix_irqs = 4U, \
.irq_mask = ~0U, \
.vecs = HW_ATL_A0_RSS_MAX, \
.tcs = HW_ATL_A0_TC_MAX, \
.rxd_alignment = 1U, \
.rxd_size = HW_ATL_A0_RXD_SIZE, \
.rxds = 248U, \
.txd_alignment = 1U, \
.txd_size = HW_ATL_A0_TXD_SIZE, \
.txds = 8U * 1024U, \
.txhwb_alignment = 4096U, \
.tx_rings = HW_ATL_A0_TX_RINGS, \
.rx_rings = HW_ATL_A0_RX_RINGS, \
.hw_features = NETIF_F_HW_CSUM | \
NETIF_F_RXHASH | \
NETIF_F_RXCSUM | \
NETIF_F_SG | \
NETIF_F_TSO, \
.hw_priv_flags = IFF_UNICAST_FLT, \
.flow_control = true, \
.mtu = HW_ATL_A0_MTU_JUMBO, \
.mac_regs_count = 88
const struct aq_hw_caps_s hw_atl_a0_caps_aqc100 = {
DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
.media_type = AQ_HW_MEDIA_TYPE_FIBRE,
.link_speed_msk = HW_ATL_A0_RATE_5G |
HW_ATL_A0_RATE_2G5 |
HW_ATL_A0_RATE_1G |
HW_ATL_A0_RATE_100M,
};
if (device == AQ_DEVICE_ID_D108 && subsystem_device == 0x0001)
aq_hw_caps->link_speed_msk &= ~AQ_NIC_RATE_10G;
const struct aq_hw_caps_s hw_atl_a0_caps_aqc107 = {
DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
.media_type = AQ_HW_MEDIA_TYPE_TP,
.link_speed_msk = HW_ATL_A0_RATE_10G |
HW_ATL_A0_RATE_5G |
HW_ATL_A0_RATE_2G5 |
HW_ATL_A0_RATE_1G |
HW_ATL_A0_RATE_100M,
};
if (device == AQ_DEVICE_ID_D109 && subsystem_device == 0x0001) {
aq_hw_caps->link_speed_msk &= ~AQ_NIC_RATE_10G;
aq_hw_caps->link_speed_msk &= ~AQ_NIC_RATE_5G;
}
const struct aq_hw_caps_s hw_atl_a0_caps_aqc108 = {
DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
.media_type = AQ_HW_MEDIA_TYPE_TP,
.link_speed_msk = HW_ATL_A0_RATE_5G |
HW_ATL_A0_RATE_2G5 |
HW_ATL_A0_RATE_1G |
HW_ATL_A0_RATE_100M,
};
const struct aq_hw_caps_s hw_atl_a0_caps_aqc109 = {
DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
.media_type = AQ_HW_MEDIA_TYPE_TP,
.link_speed_msk = HW_ATL_A0_RATE_2G5 |
HW_ATL_A0_RATE_1G |
HW_ATL_A0_RATE_100M,
};
return 0;
}
static struct aq_hw_s *hw_atl_a0_create(struct aq_pci_func_s *aq_pci_func,
unsigned int port)
......@@ -861,11 +905,9 @@ static int hw_atl_a0_hw_set_speed(struct aq_hw_s *self, u32 speed)
return err;
}
static const struct aq_hw_ops hw_atl_ops_ = {
const struct aq_hw_ops hw_atl_ops_a0 = {
.create = hw_atl_a0_create,
.destroy = hw_atl_a0_destroy,
.get_hw_caps = hw_atl_a0_get_hw_caps,
.hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
.hw_set_mac_address = hw_atl_a0_hw_mac_addr_set,
.hw_get_link_status = hw_atl_utils_mpi_get_link_status,
......@@ -903,17 +945,3 @@ static const struct aq_hw_ops hw_atl_ops_ = {
.hw_get_hw_stats = hw_atl_utils_get_hw_stats,
.hw_get_fw_version = hw_atl_utils_get_fw_version,
};
const struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev)
{
bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
bool is_did_ok = ((pdev->device == AQ_DEVICE_ID_0001) ||
(pdev->device == AQ_DEVICE_ID_D100) ||
(pdev->device == AQ_DEVICE_ID_D107) ||
(pdev->device == AQ_DEVICE_ID_D108) ||
(pdev->device == AQ_DEVICE_ID_D109));
bool is_rev_ok = (pdev->revision == 1U);
return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;
}
......@@ -16,6 +16,11 @@
#include "../aq_common.h"
const struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev);
extern const struct aq_hw_caps_s hw_atl_a0_caps_aqc100;
extern const struct aq_hw_caps_s hw_atl_a0_caps_aqc107;
extern const struct aq_hw_caps_s hw_atl_a0_caps_aqc108;
extern const struct aq_hw_caps_s hw_atl_a0_caps_aqc109;
extern const struct aq_hw_ops hw_atl_ops_a0;
#endif /* HW_ATL_A0_H */
......@@ -62,6 +62,12 @@
#define HW_ATL_A0_MPI_SPEED_MSK 0xFFFFU
#define HW_ATL_A0_MPI_SPEED_SHIFT 16U
#define HW_ATL_A0_RATE_10G BIT(0)
#define HW_ATL_A0_RATE_5G BIT(1)
#define HW_ATL_A0_RATE_2G5 BIT(3)
#define HW_ATL_A0_RATE_1G BIT(4)
#define HW_ATL_A0_RATE_100M BIT(5)
#define HW_ATL_A0_TXBUF_MAX 160U
#define HW_ATL_A0_RXBUF_MAX 320U
......@@ -82,38 +88,4 @@
#define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U
/* HW layer capabilities */
static struct aq_hw_caps_s hw_atl_a0_hw_caps_ = {
.ports = 1U,
.is_64_dma = true,
.msix_irqs = 4U,
.irq_mask = ~0U,
.vecs = HW_ATL_A0_RSS_MAX,
.tcs = HW_ATL_A0_TC_MAX,
.rxd_alignment = 1U,
.rxd_size = HW_ATL_A0_RXD_SIZE,
.rxds = 248U,
.txd_alignment = 1U,
.txd_size = HW_ATL_A0_TXD_SIZE,
.txds = 8U * 1024U,
.txhwb_alignment = 4096U,
.tx_rings = HW_ATL_A0_TX_RINGS,
.rx_rings = HW_ATL_A0_RX_RINGS,
.hw_features = NETIF_F_HW_CSUM |
NETIF_F_RXCSUM |
NETIF_F_RXHASH |
NETIF_F_SG |
NETIF_F_TSO,
.hw_priv_flags = IFF_UNICAST_FLT,
.link_speed_msk = (AQ_NIC_RATE_10G |
AQ_NIC_RATE_5G |
AQ_NIC_RATE_2GS |
AQ_NIC_RATE_1G |
AQ_NIC_RATE_100M),
.flow_control = true,
.mtu = HW_ATL_A0_MTU_JUMBO,
.mac_regs_count = 88,
.fw_ver_expected = HW_ATL_A0_FW_VER_EXPECTED,
};
#endif /* HW_ATL_A0_INTERNAL_H */
......@@ -19,23 +19,68 @@
#include "hw_atl_b0_internal.h"
#include "hw_atl_llh_internal.h"
static int hw_atl_b0_get_hw_caps(struct aq_hw_s *self,
struct aq_hw_caps_s *aq_hw_caps,
unsigned short device,
unsigned short subsystem_device)
{
memcpy(aq_hw_caps, &hw_atl_b0_hw_caps_, sizeof(*aq_hw_caps));
#define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \
.is_64_dma = true, \
.msix_irqs = 4U, \
.irq_mask = ~0U, \
.vecs = HW_ATL_B0_RSS_MAX, \
.tcs = HW_ATL_B0_TC_MAX, \
.rxd_alignment = 1U, \
.rxd_size = HW_ATL_B0_RXD_SIZE, \
.rxds = 4U * 1024U, \
.txd_alignment = 1U, \
.txd_size = HW_ATL_B0_TXD_SIZE, \
.txds = 8U * 1024U, \
.txhwb_alignment = 4096U, \
.tx_rings = HW_ATL_B0_TX_RINGS, \
.rx_rings = HW_ATL_B0_RX_RINGS, \
.hw_features = NETIF_F_HW_CSUM | \
NETIF_F_RXCSUM | \
NETIF_F_RXHASH | \
NETIF_F_SG | \
NETIF_F_TSO | \
NETIF_F_LRO, \
.hw_priv_flags = IFF_UNICAST_FLT, \
.flow_control = true, \
.mtu = HW_ATL_B0_MTU_JUMBO, \
.mac_regs_count = 88
const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = {
DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
.media_type = AQ_HW_MEDIA_TYPE_FIBRE,
.link_speed_msk = HW_ATL_B0_RATE_10G |
HW_ATL_B0_RATE_5G |
HW_ATL_B0_RATE_2G5 |
HW_ATL_B0_RATE_1G |
HW_ATL_B0_RATE_100M,
};
if (device == AQ_DEVICE_ID_D108 && subsystem_device == 0x0001)
aq_hw_caps->link_speed_msk &= ~AQ_NIC_RATE_10G;
const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = {
DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
.media_type = AQ_HW_MEDIA_TYPE_TP,
.link_speed_msk = HW_ATL_B0_RATE_10G |
HW_ATL_B0_RATE_5G |
HW_ATL_B0_RATE_2G5 |
HW_ATL_B0_RATE_1G |
HW_ATL_B0_RATE_100M,
};
if (device == AQ_DEVICE_ID_D109 && subsystem_device == 0x0001) {
aq_hw_caps->link_speed_msk &= ~AQ_NIC_RATE_10G;
aq_hw_caps->link_speed_msk &= ~AQ_NIC_RATE_5G;
}
const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = {
DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
.media_type = AQ_HW_MEDIA_TYPE_TP,
.link_speed_msk = HW_ATL_B0_RATE_5G |
HW_ATL_B0_RATE_2G5 |
HW_ATL_B0_RATE_1G |
HW_ATL_B0_RATE_100M,
};
return 0;
}
const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = {
DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
.media_type = AQ_HW_MEDIA_TYPE_TP,
.link_speed_msk = HW_ATL_B0_RATE_2G5 |
HW_ATL_B0_RATE_1G |
HW_ATL_B0_RATE_100M,
};
static struct aq_hw_s *hw_atl_b0_create(struct aq_pci_func_s *aq_pci_func,
unsigned int port)
......@@ -935,11 +980,9 @@ static int hw_atl_b0_hw_set_speed(struct aq_hw_s *self, u32 speed)
return err;
}
static const struct aq_hw_ops hw_atl_ops_ = {
const struct aq_hw_ops hw_atl_ops_b0 = {
.create = hw_atl_b0_create,
.destroy = hw_atl_b0_destroy,
.get_hw_caps = hw_atl_b0_get_hw_caps,
.hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
.hw_set_mac_address = hw_atl_b0_hw_mac_addr_set,
.hw_get_link_status = hw_atl_utils_mpi_get_link_status,
......@@ -977,17 +1020,3 @@ static const struct aq_hw_ops hw_atl_ops_ = {
.hw_get_hw_stats = hw_atl_utils_get_hw_stats,
.hw_get_fw_version = hw_atl_utils_get_fw_version,
};
const struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev)
{
bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
bool is_did_ok = ((pdev->device == AQ_DEVICE_ID_0001) ||
(pdev->device == AQ_DEVICE_ID_D100) ||
(pdev->device == AQ_DEVICE_ID_D107) ||
(pdev->device == AQ_DEVICE_ID_D108) ||
(pdev->device == AQ_DEVICE_ID_D109));
bool is_rev_ok = (pdev->revision == 2U);
return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;
}
......@@ -16,6 +16,27 @@
#include "../aq_common.h"
const struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev);
extern const struct aq_hw_caps_s hw_atl_b0_caps_aqc100;
extern const struct aq_hw_caps_s hw_atl_b0_caps_aqc107;
extern const struct aq_hw_caps_s hw_atl_b0_caps_aqc108;
extern const struct aq_hw_caps_s hw_atl_b0_caps_aqc109;
#define hw_atl_b0_caps_aqc111 hw_atl_b0_caps_aqc108
#define hw_atl_b0_caps_aqc112 hw_atl_b0_caps_aqc109
#define hw_atl_b0_caps_aqc100s hw_atl_b0_caps_aqc100
#define hw_atl_b0_caps_aqc107s hw_atl_b0_caps_aqc107
#define hw_atl_b0_caps_aqc108s hw_atl_b0_caps_aqc108
#define hw_atl_b0_caps_aqc109s hw_atl_b0_caps_aqc109
#define hw_atl_b0_caps_aqc111s hw_atl_b0_caps_aqc108
#define hw_atl_b0_caps_aqc112s hw_atl_b0_caps_aqc109
#define hw_atl_b0_caps_aqc111e hw_atl_b0_caps_aqc108
#define hw_atl_b0_caps_aqc112e hw_atl_b0_caps_aqc109
extern const struct aq_hw_ops hw_atl_ops_b0;
#define hw_atl_ops_b1 hw_atl_ops_b0
#endif /* HW_ATL_B0_H */
......@@ -67,6 +67,12 @@
#define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU
#define HW_ATL_B0_MPI_SPEED_SHIFT 16U
#define HW_ATL_B0_RATE_10G BIT(0)
#define HW_ATL_B0_RATE_5G BIT(1)
#define HW_ATL_B0_RATE_2G5 BIT(3)
#define HW_ATL_B0_RATE_1G BIT(4)
#define HW_ATL_B0_RATE_100M BIT(5)
#define HW_ATL_B0_TXBUF_MAX 160U
#define HW_ATL_B0_RXBUF_MAX 320U
......@@ -137,38 +143,5 @@
#define HW_ATL_INTR_MODER_MIN 0xFF
/* HW layer capabilities */
static struct aq_hw_caps_s hw_atl_b0_hw_caps_ = {
.ports = 1U,
.is_64_dma = true,
.msix_irqs = 4U,
.irq_mask = ~0U,
.vecs = HW_ATL_B0_RSS_MAX,
.tcs = HW_ATL_B0_TC_MAX,
.rxd_alignment = 1U,
.rxd_size = HW_ATL_B0_RXD_SIZE,
.rxds = 8U * 1024U,
.txd_alignment = 1U,
.txd_size = HW_ATL_B0_TXD_SIZE,
.txds = 8U * 1024U,
.txhwb_alignment = 4096U,
.tx_rings = HW_ATL_B0_TX_RINGS,
.rx_rings = HW_ATL_B0_RX_RINGS,
.hw_features = NETIF_F_HW_CSUM |
NETIF_F_RXCSUM |
NETIF_F_RXHASH |
NETIF_F_SG |
NETIF_F_TSO |
NETIF_F_LRO,
.hw_priv_flags = IFF_UNICAST_FLT,
.link_speed_msk = (AQ_NIC_RATE_10G |
AQ_NIC_RATE_5G |
AQ_NIC_RATE_2GS |
AQ_NIC_RATE_1G |
AQ_NIC_RATE_100M),
.flow_control = true,
.mtu = HW_ATL_B0_MTU_JUMBO,
.mac_regs_count = 88,
.fw_ver_expected = HW_ATL_B0_FW_VER_EXPECTED,
};
#endif /* HW_ATL_B0_INTERNAL_H */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment