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nexedi
linux
Commits
49dea76a
Commit
49dea76a
authored
Jan 02, 2016
by
Michael Turquette
Browse files
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Plain Diff
Merge branch 'clk-rockchip' into clk-next
parents
0b2e7886
5b738403
Changes
4
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4 changed files
with
116 additions
and
47 deletions
+116
-47
drivers/clk/rockchip/clk-rk3036.c
drivers/clk/rockchip/clk-rk3036.c
+25
-10
drivers/clk/rockchip/clk-rk3188.c
drivers/clk/rockchip/clk-rk3188.c
+50
-20
drivers/clk/rockchip/clk-rk3288.c
drivers/clk/rockchip/clk-rk3288.c
+40
-16
drivers/clk/rockchip/clk.h
drivers/clk/rockchip/clk.h
+1
-1
No files found.
drivers/clk/rockchip/clk-rk3036.c
View file @
49dea76a
...
@@ -149,6 +149,26 @@ static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = {
...
@@ -149,6 +149,26 @@ static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = {
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
static
struct
rockchip_clk_branch
rk3036_uart0_fracmux
__initdata
=
MUX
(
SCLK_UART0
,
"sclk_uart0"
,
mux_uart0_p
,
CLK_SET_RATE_PARENT
,
RK2928_CLKSEL_CON
(
13
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3036_uart1_fracmux
__initdata
=
MUX
(
SCLK_UART1
,
"sclk_uart1"
,
mux_uart1_p
,
CLK_SET_RATE_PARENT
,
RK2928_CLKSEL_CON
(
14
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3036_uart2_fracmux
__initdata
=
MUX
(
SCLK_UART2
,
"sclk_uart2"
,
mux_uart2_p
,
CLK_SET_RATE_PARENT
,
RK2928_CLKSEL_CON
(
15
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3036_i2s_fracmux
__initdata
=
MUX
(
0
,
"i2s_pre"
,
mux_i2s_pre_p
,
CLK_SET_RATE_PARENT
,
RK2928_CLKSEL_CON
(
3
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3036_spdif_fracmux
__initdata
=
MUX
(
SCLK_SPDIF
,
"sclk_spdif"
,
mux_spdif_p
,
0
,
RK2928_CLKSEL_CON
(
5
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3036_clk_branches
[]
__initdata
=
{
static
struct
rockchip_clk_branch
rk3036_clk_branches
[]
__initdata
=
{
/*
/*
* Clock-Architecture Diagram 1
* Clock-Architecture Diagram 1
...
@@ -230,18 +250,15 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
...
@@ -230,18 +250,15 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"uart0_frac"
,
"uart0_src"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"uart0_frac"
,
"uart0_src"
,
CLK_SET_RATE_PARENT
,
RK2928_CLKSEL_CON
(
17
),
0
,
RK2928_CLKSEL_CON
(
17
),
0
,
RK2928_CLKGATE_CON
(
1
),
9
,
GFLAGS
,
RK2928_CLKGATE_CON
(
1
),
9
,
GFLAGS
,
MUX
(
SCLK_UART0
,
"sclk_uart0"
,
mux_uart0_p
,
CLK_SET_RATE_PARENT
,
&
rk3036_uart0_fracmux
),
RK2928_CLKSEL_CON
(
13
),
8
,
2
,
MFLAGS
)),
COMPOSITE_FRACMUX
(
0
,
"uart1_frac"
,
"uart1_src"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"uart1_frac"
,
"uart1_src"
,
CLK_SET_RATE_PARENT
,
RK2928_CLKSEL_CON
(
18
),
0
,
RK2928_CLKSEL_CON
(
18
),
0
,
RK2928_CLKGATE_CON
(
1
),
11
,
GFLAGS
,
RK2928_CLKGATE_CON
(
1
),
11
,
GFLAGS
,
MUX
(
SCLK_UART1
,
"sclk_uart1"
,
mux_uart1_p
,
CLK_SET_RATE_PARENT
,
&
rk3036_uart1_fracmux
),
RK2928_CLKSEL_CON
(
14
),
8
,
2
,
MFLAGS
)),
COMPOSITE_FRACMUX
(
0
,
"uart2_frac"
,
"uart2_src"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"uart2_frac"
,
"uart2_src"
,
CLK_SET_RATE_PARENT
,
RK2928_CLKSEL_CON
(
19
),
0
,
RK2928_CLKSEL_CON
(
19
),
0
,
RK2928_CLKGATE_CON
(
1
),
13
,
GFLAGS
,
RK2928_CLKGATE_CON
(
1
),
13
,
GFLAGS
,
MUX
(
SCLK_UART2
,
"sclk_uart2"
,
mux_uart2_p
,
CLK_SET_RATE_PARENT
,
&
rk3036_uart2_fracmux
),
RK2928_CLKSEL_CON
(
15
),
8
,
2
,
MFLAGS
)),
COMPOSITE
(
0
,
"aclk_vcodec"
,
mux_pll_src_3plls_p
,
0
,
COMPOSITE
(
0
,
"aclk_vcodec"
,
mux_pll_src_3plls_p
,
0
,
RK2928_CLKSEL_CON
(
32
),
14
,
2
,
MFLAGS
,
8
,
5
,
DFLAGS
,
RK2928_CLKSEL_CON
(
32
),
14
,
2
,
MFLAGS
,
8
,
5
,
DFLAGS
,
...
@@ -292,8 +309,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
...
@@ -292,8 +309,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"i2s_frac"
,
"i2s_src"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"i2s_frac"
,
"i2s_src"
,
CLK_SET_RATE_PARENT
,
RK2928_CLKSEL_CON
(
7
),
0
,
RK2928_CLKSEL_CON
(
7
),
0
,
RK2928_CLKGATE_CON
(
0
),
10
,
GFLAGS
,
RK2928_CLKGATE_CON
(
0
),
10
,
GFLAGS
,
MUX
(
0
,
"i2s_pre"
,
mux_i2s_pre_p
,
CLK_SET_RATE_PARENT
,
&
rk3036_i2s_fracmux
),
RK2928_CLKSEL_CON
(
3
),
8
,
2
,
MFLAGS
)),
COMPOSITE_NODIV
(
SCLK_I2S_OUT
,
"i2s_clkout"
,
mux_i2s_clkout_p
,
0
,
COMPOSITE_NODIV
(
SCLK_I2S_OUT
,
"i2s_clkout"
,
mux_i2s_clkout_p
,
0
,
RK2928_CLKSEL_CON
(
3
),
12
,
1
,
MFLAGS
,
RK2928_CLKSEL_CON
(
3
),
12
,
1
,
MFLAGS
,
RK2928_CLKGATE_CON
(
0
),
13
,
GFLAGS
),
RK2928_CLKGATE_CON
(
0
),
13
,
GFLAGS
),
...
@@ -306,8 +322,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
...
@@ -306,8 +322,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"spdif_frac"
,
"spdif_src"
,
0
,
COMPOSITE_FRACMUX
(
0
,
"spdif_frac"
,
"spdif_src"
,
0
,
RK2928_CLKSEL_CON
(
9
),
0
,
RK2928_CLKSEL_CON
(
9
),
0
,
RK2928_CLKGATE_CON
(
2
),
12
,
GFLAGS
,
RK2928_CLKGATE_CON
(
2
),
12
,
GFLAGS
,
MUX
(
SCLK_SPDIF
,
"sclk_spdif"
,
mux_spdif_p
,
0
,
&
rk3036_spdif_fracmux
),
RK2928_CLKSEL_CON
(
5
),
8
,
2
,
MFLAGS
)),
GATE
(
SCLK_OTGPHY0
,
"sclk_otgphy0"
,
"xin12m"
,
CLK_IGNORE_UNUSED
,
GATE
(
SCLK_OTGPHY0
,
"sclk_otgphy0"
,
"xin12m"
,
CLK_IGNORE_UNUSED
,
RK2928_CLKGATE_CON
(
1
),
5
,
GFLAGS
),
RK2928_CLKGATE_CON
(
1
),
5
,
GFLAGS
),
...
...
drivers/clk/rockchip/clk-rk3188.c
View file @
49dea76a
...
@@ -247,6 +247,30 @@ static struct clk_div_table div_core_peri_t[] = {
...
@@ -247,6 +247,30 @@ static struct clk_div_table div_core_peri_t[] = {
{
/* sentinel */
},
{
/* sentinel */
},
};
};
static
struct
rockchip_clk_branch
common_hsadc_out_fracmux
__initdata
=
MUX
(
0
,
"sclk_hsadc_out"
,
mux_sclk_hsadc_p
,
0
,
RK2928_CLKSEL_CON
(
22
),
4
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
common_spdif_fracmux
__initdata
=
MUX
(
SCLK_SPDIF
,
"sclk_spdif"
,
mux_sclk_spdif_p
,
CLK_SET_RATE_PARENT
,
RK2928_CLKSEL_CON
(
5
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
common_uart0_fracmux
__initdata
=
MUX
(
SCLK_UART0
,
"sclk_uart0"
,
mux_sclk_uart0_p
,
0
,
RK2928_CLKSEL_CON
(
13
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
common_uart1_fracmux
__initdata
=
MUX
(
SCLK_UART1
,
"sclk_uart1"
,
mux_sclk_uart1_p
,
0
,
RK2928_CLKSEL_CON
(
14
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
common_uart2_fracmux
__initdata
=
MUX
(
SCLK_UART2
,
"sclk_uart2"
,
mux_sclk_uart2_p
,
0
,
RK2928_CLKSEL_CON
(
15
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
common_uart3_fracmux
__initdata
=
MUX
(
SCLK_UART3
,
"sclk_uart3"
,
mux_sclk_uart3_p
,
0
,
RK2928_CLKSEL_CON
(
16
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
common_clk_branches
[]
__initdata
=
{
static
struct
rockchip_clk_branch
common_clk_branches
[]
__initdata
=
{
/*
/*
* Clock-Architecture Diagram 2
* Clock-Architecture Diagram 2
...
@@ -338,8 +362,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
...
@@ -338,8 +362,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"hsadc_frac"
,
"hsadc_src"
,
0
,
COMPOSITE_FRACMUX
(
0
,
"hsadc_frac"
,
"hsadc_src"
,
0
,
RK2928_CLKSEL_CON
(
23
),
0
,
RK2928_CLKSEL_CON
(
23
),
0
,
RK2928_CLKGATE_CON
(
2
),
7
,
GFLAGS
,
RK2928_CLKGATE_CON
(
2
),
7
,
GFLAGS
,
MUX
(
0
,
"sclk_hsadc_out"
,
mux_sclk_hsadc_p
,
0
,
&
common_hsadc_out_fracmux
),
RK2928_CLKSEL_CON
(
22
),
4
,
2
,
MFLAGS
)),
INVERTER
(
SCLK_HSADC
,
"sclk_hsadc"
,
"sclk_hsadc_out"
,
INVERTER
(
SCLK_HSADC
,
"sclk_hsadc"
,
"sclk_hsadc_out"
,
RK2928_CLKSEL_CON
(
22
),
7
,
IFLAGS
),
RK2928_CLKSEL_CON
(
22
),
7
,
IFLAGS
),
...
@@ -353,8 +376,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
...
@@ -353,8 +376,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"spdif_frac"
,
"spdif_pll"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"spdif_frac"
,
"spdif_pll"
,
CLK_SET_RATE_PARENT
,
RK2928_CLKSEL_CON
(
9
),
0
,
RK2928_CLKSEL_CON
(
9
),
0
,
RK2928_CLKGATE_CON
(
0
),
14
,
GFLAGS
,
RK2928_CLKGATE_CON
(
0
),
14
,
GFLAGS
,
MUX
(
SCLK_SPDIF
,
"sclk_spdif"
,
mux_sclk_spdif_p
,
CLK_SET_RATE_PARENT
,
&
common_spdif_fracmux
),
RK2928_CLKSEL_CON
(
5
),
8
,
2
,
MFLAGS
)),
/*
/*
* Clock-Architecture Diagram 4
* Clock-Architecture Diagram 4
...
@@ -388,32 +410,28 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
...
@@ -388,32 +410,28 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"uart0_frac"
,
"uart0_pre"
,
0
,
COMPOSITE_FRACMUX
(
0
,
"uart0_frac"
,
"uart0_pre"
,
0
,
RK2928_CLKSEL_CON
(
17
),
0
,
RK2928_CLKSEL_CON
(
17
),
0
,
RK2928_CLKGATE_CON
(
1
),
9
,
GFLAGS
,
RK2928_CLKGATE_CON
(
1
),
9
,
GFLAGS
,
MUX
(
SCLK_UART0
,
"sclk_uart0"
,
mux_sclk_uart0_p
,
0
,
&
common_uart0_fracmux
),
RK2928_CLKSEL_CON
(
13
),
8
,
2
,
MFLAGS
)),
COMPOSITE_NOMUX
(
0
,
"uart1_pre"
,
"uart_src"
,
0
,
COMPOSITE_NOMUX
(
0
,
"uart1_pre"
,
"uart_src"
,
0
,
RK2928_CLKSEL_CON
(
14
),
0
,
7
,
DFLAGS
,
RK2928_CLKSEL_CON
(
14
),
0
,
7
,
DFLAGS
,
RK2928_CLKGATE_CON
(
1
),
10
,
GFLAGS
),
RK2928_CLKGATE_CON
(
1
),
10
,
GFLAGS
),
COMPOSITE_FRACMUX
(
0
,
"uart1_frac"
,
"uart1_pre"
,
0
,
COMPOSITE_FRACMUX
(
0
,
"uart1_frac"
,
"uart1_pre"
,
0
,
RK2928_CLKSEL_CON
(
18
),
0
,
RK2928_CLKSEL_CON
(
18
),
0
,
RK2928_CLKGATE_CON
(
1
),
11
,
GFLAGS
,
RK2928_CLKGATE_CON
(
1
),
11
,
GFLAGS
,
MUX
(
SCLK_UART1
,
"sclk_uart1"
,
mux_sclk_uart1_p
,
0
,
&
common_uart1_fracmux
),
RK2928_CLKSEL_CON
(
14
),
8
,
2
,
MFLAGS
)),
COMPOSITE_NOMUX
(
0
,
"uart2_pre"
,
"uart_src"
,
0
,
COMPOSITE_NOMUX
(
0
,
"uart2_pre"
,
"uart_src"
,
0
,
RK2928_CLKSEL_CON
(
15
),
0
,
7
,
DFLAGS
,
RK2928_CLKSEL_CON
(
15
),
0
,
7
,
DFLAGS
,
RK2928_CLKGATE_CON
(
1
),
12
,
GFLAGS
),
RK2928_CLKGATE_CON
(
1
),
12
,
GFLAGS
),
COMPOSITE_FRACMUX
(
0
,
"uart2_frac"
,
"uart2_pre"
,
0
,
COMPOSITE_FRACMUX
(
0
,
"uart2_frac"
,
"uart2_pre"
,
0
,
RK2928_CLKSEL_CON
(
19
),
0
,
RK2928_CLKSEL_CON
(
19
),
0
,
RK2928_CLKGATE_CON
(
1
),
13
,
GFLAGS
,
RK2928_CLKGATE_CON
(
1
),
13
,
GFLAGS
,
MUX
(
SCLK_UART2
,
"sclk_uart2"
,
mux_sclk_uart2_p
,
0
,
&
common_uart2_fracmux
),
RK2928_CLKSEL_CON
(
15
),
8
,
2
,
MFLAGS
)),
COMPOSITE_NOMUX
(
0
,
"uart3_pre"
,
"uart_src"
,
0
,
COMPOSITE_NOMUX
(
0
,
"uart3_pre"
,
"uart_src"
,
0
,
RK2928_CLKSEL_CON
(
16
),
0
,
7
,
DFLAGS
,
RK2928_CLKSEL_CON
(
16
),
0
,
7
,
DFLAGS
,
RK2928_CLKGATE_CON
(
1
),
14
,
GFLAGS
),
RK2928_CLKGATE_CON
(
1
),
14
,
GFLAGS
),
COMPOSITE_FRACMUX
(
0
,
"uart3_frac"
,
"uart3_pre"
,
0
,
COMPOSITE_FRACMUX
(
0
,
"uart3_frac"
,
"uart3_pre"
,
0
,
RK2928_CLKSEL_CON
(
20
),
0
,
RK2928_CLKSEL_CON
(
20
),
0
,
RK2928_CLKGATE_CON
(
1
),
15
,
GFLAGS
,
RK2928_CLKGATE_CON
(
1
),
15
,
GFLAGS
,
MUX
(
SCLK_UART3
,
"sclk_uart3"
,
mux_sclk_uart3_p
,
0
,
&
common_uart3_fracmux
),
RK2928_CLKSEL_CON
(
16
),
8
,
2
,
MFLAGS
)),
GATE
(
SCLK_JTAG
,
"jtag"
,
"ext_jtag"
,
0
,
RK2928_CLKGATE_CON
(
1
),
3
,
GFLAGS
),
GATE
(
SCLK_JTAG
,
"jtag"
,
"ext_jtag"
,
0
,
RK2928_CLKGATE_CON
(
1
),
3
,
GFLAGS
),
...
@@ -523,6 +541,18 @@ static struct clk_div_table div_aclk_cpu_t[] = {
...
@@ -523,6 +541,18 @@ static struct clk_div_table div_aclk_cpu_t[] = {
{
/* sentinel */
},
{
/* sentinel */
},
};
};
static
struct
rockchip_clk_branch
rk3066a_i2s0_fracmux
__initdata
=
MUX
(
SCLK_I2S0
,
"sclk_i2s0"
,
mux_sclk_i2s0_p
,
0
,
RK2928_CLKSEL_CON
(
2
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3066a_i2s1_fracmux
__initdata
=
MUX
(
SCLK_I2S1
,
"sclk_i2s1"
,
mux_sclk_i2s1_p
,
0
,
RK2928_CLKSEL_CON
(
3
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3066a_i2s2_fracmux
__initdata
=
MUX
(
SCLK_I2S2
,
"sclk_i2s2"
,
mux_sclk_i2s2_p
,
0
,
RK2928_CLKSEL_CON
(
4
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3066a_clk_branches
[]
__initdata
=
{
static
struct
rockchip_clk_branch
rk3066a_clk_branches
[]
__initdata
=
{
DIVTBL
(
0
,
"aclk_cpu_pre"
,
"armclk"
,
0
,
DIVTBL
(
0
,
"aclk_cpu_pre"
,
"armclk"
,
0
,
RK2928_CLKSEL_CON
(
1
),
0
,
3
,
DFLAGS
|
CLK_DIVIDER_READ_ONLY
,
div_aclk_cpu_t
),
RK2928_CLKSEL_CON
(
1
),
0
,
3
,
DFLAGS
|
CLK_DIVIDER_READ_ONLY
,
div_aclk_cpu_t
),
...
@@ -587,24 +617,21 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
...
@@ -587,24 +617,21 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"i2s0_frac"
,
"i2s0_pre"
,
0
,
COMPOSITE_FRACMUX
(
0
,
"i2s0_frac"
,
"i2s0_pre"
,
0
,
RK2928_CLKSEL_CON
(
6
),
0
,
RK2928_CLKSEL_CON
(
6
),
0
,
RK2928_CLKGATE_CON
(
0
),
8
,
GFLAGS
,
RK2928_CLKGATE_CON
(
0
),
8
,
GFLAGS
,
MUX
(
SCLK_I2S0
,
"sclk_i2s0"
,
mux_sclk_i2s0_p
,
0
,
&
rk3066a_i2s0_fracmux
),
RK2928_CLKSEL_CON
(
2
),
8
,
2
,
MFLAGS
)),
COMPOSITE_NOMUX
(
0
,
"i2s1_pre"
,
"i2s_src"
,
0
,
COMPOSITE_NOMUX
(
0
,
"i2s1_pre"
,
"i2s_src"
,
0
,
RK2928_CLKSEL_CON
(
3
),
0
,
7
,
DFLAGS
,
RK2928_CLKSEL_CON
(
3
),
0
,
7
,
DFLAGS
,
RK2928_CLKGATE_CON
(
0
),
9
,
GFLAGS
),
RK2928_CLKGATE_CON
(
0
),
9
,
GFLAGS
),
COMPOSITE_FRACMUX
(
0
,
"i2s1_frac"
,
"i2s1_pre"
,
0
,
COMPOSITE_FRACMUX
(
0
,
"i2s1_frac"
,
"i2s1_pre"
,
0
,
RK2928_CLKSEL_CON
(
7
),
0
,
RK2928_CLKSEL_CON
(
7
),
0
,
RK2928_CLKGATE_CON
(
0
),
10
,
GFLAGS
,
RK2928_CLKGATE_CON
(
0
),
10
,
GFLAGS
,
MUX
(
SCLK_I2S1
,
"sclk_i2s1"
,
mux_sclk_i2s1_p
,
0
,
&
rk3066a_i2s1_fracmux
),
RK2928_CLKSEL_CON
(
3
),
8
,
2
,
MFLAGS
)),
COMPOSITE_NOMUX
(
0
,
"i2s2_pre"
,
"i2s_src"
,
0
,
COMPOSITE_NOMUX
(
0
,
"i2s2_pre"
,
"i2s_src"
,
0
,
RK2928_CLKSEL_CON
(
4
),
0
,
7
,
DFLAGS
,
RK2928_CLKSEL_CON
(
4
),
0
,
7
,
DFLAGS
,
RK2928_CLKGATE_CON
(
0
),
11
,
GFLAGS
),
RK2928_CLKGATE_CON
(
0
),
11
,
GFLAGS
),
COMPOSITE_FRACMUX
(
0
,
"i2s2_frac"
,
"i2s2_pre"
,
0
,
COMPOSITE_FRACMUX
(
0
,
"i2s2_frac"
,
"i2s2_pre"
,
0
,
RK2928_CLKSEL_CON
(
8
),
0
,
RK2928_CLKSEL_CON
(
8
),
0
,
RK2928_CLKGATE_CON
(
0
),
12
,
GFLAGS
,
RK2928_CLKGATE_CON
(
0
),
12
,
GFLAGS
,
MUX
(
SCLK_I2S2
,
"sclk_i2s2"
,
mux_sclk_i2s2_p
,
0
,
&
rk3066a_i2s2_fracmux
),
RK2928_CLKSEL_CON
(
4
),
8
,
2
,
MFLAGS
)),
GATE
(
HCLK_I2S1
,
"hclk_i2s1"
,
"hclk_cpu"
,
0
,
RK2928_CLKGATE_CON
(
7
),
3
,
GFLAGS
),
GATE
(
HCLK_I2S1
,
"hclk_i2s1"
,
"hclk_cpu"
,
0
,
RK2928_CLKGATE_CON
(
7
),
3
,
GFLAGS
),
GATE
(
HCLK_I2S2
,
"hclk_i2s2"
,
"hclk_cpu"
,
0
,
RK2928_CLKGATE_CON
(
7
),
4
,
GFLAGS
),
GATE
(
HCLK_I2S2
,
"hclk_i2s2"
,
"hclk_cpu"
,
0
,
RK2928_CLKGATE_CON
(
7
),
4
,
GFLAGS
),
...
@@ -638,6 +665,10 @@ static struct clk_div_table div_rk3188_aclk_core_t[] = {
...
@@ -638,6 +665,10 @@ static struct clk_div_table div_rk3188_aclk_core_t[] = {
PNAME
(
mux_hsicphy_p
)
=
{
"sclk_otgphy0"
,
"sclk_otgphy1"
,
PNAME
(
mux_hsicphy_p
)
=
{
"sclk_otgphy0"
,
"sclk_otgphy1"
,
"gpll"
,
"cpll"
};
"gpll"
,
"cpll"
};
static
struct
rockchip_clk_branch
rk3188_i2s0_fracmux
__initdata
=
MUX
(
SCLK_I2S0
,
"sclk_i2s0"
,
mux_sclk_i2s0_p
,
0
,
RK2928_CLKSEL_CON
(
3
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3188_clk_branches
[]
__initdata
=
{
static
struct
rockchip_clk_branch
rk3188_clk_branches
[]
__initdata
=
{
COMPOSITE_NOMUX_DIVTBL
(
0
,
"aclk_core"
,
"armclk"
,
CLK_IGNORE_UNUSED
,
COMPOSITE_NOMUX_DIVTBL
(
0
,
"aclk_core"
,
"armclk"
,
CLK_IGNORE_UNUSED
,
RK2928_CLKSEL_CON
(
1
),
3
,
3
,
DFLAGS
|
CLK_DIVIDER_READ_ONLY
,
RK2928_CLKSEL_CON
(
1
),
3
,
3
,
DFLAGS
|
CLK_DIVIDER_READ_ONLY
,
...
@@ -694,8 +725,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
...
@@ -694,8 +725,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"i2s0_frac"
,
"i2s0_pre"
,
0
,
COMPOSITE_FRACMUX
(
0
,
"i2s0_frac"
,
"i2s0_pre"
,
0
,
RK2928_CLKSEL_CON
(
7
),
0
,
RK2928_CLKSEL_CON
(
7
),
0
,
RK2928_CLKGATE_CON
(
0
),
10
,
GFLAGS
,
RK2928_CLKGATE_CON
(
0
),
10
,
GFLAGS
,
MUX
(
SCLK_I2S0
,
"sclk_i2s0"
,
mux_sclk_i2s0_p
,
0
,
&
rk3188_i2s0_fracmux
),
RK2928_CLKSEL_CON
(
3
),
8
,
2
,
MFLAGS
)),
GATE
(
0
,
"hclk_imem0"
,
"hclk_cpu"
,
0
,
RK2928_CLKGATE_CON
(
4
),
14
,
GFLAGS
),
GATE
(
0
,
"hclk_imem0"
,
"hclk_cpu"
,
0
,
RK2928_CLKGATE_CON
(
4
),
14
,
GFLAGS
),
GATE
(
0
,
"hclk_imem1"
,
"hclk_cpu"
,
0
,
RK2928_CLKGATE_CON
(
4
),
15
,
GFLAGS
),
GATE
(
0
,
"hclk_imem1"
,
"hclk_cpu"
,
0
,
RK2928_CLKGATE_CON
(
4
),
15
,
GFLAGS
),
...
...
drivers/clk/rockchip/clk-rk3288.c
View file @
49dea76a
...
@@ -225,6 +225,38 @@ static struct clk_div_table div_hclk_cpu_t[] = {
...
@@ -225,6 +225,38 @@ static struct clk_div_table div_hclk_cpu_t[] = {
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
static
struct
rockchip_clk_branch
rk3288_i2s_fracmux
__initdata
=
MUX
(
0
,
"i2s_pre"
,
mux_i2s_pre_p
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
4
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3288_spdif_fracmux
__initdata
=
MUX
(
0
,
"spdif_mux"
,
mux_spdif_p
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
5
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3288_spdif_8ch_fracmux
__initdata
=
MUX
(
0
,
"spdif_8ch_mux"
,
mux_spdif_8ch_p
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
40
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3288_uart0_fracmux
__initdata
=
MUX
(
SCLK_UART0
,
"sclk_uart0"
,
mux_uart0_p
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
13
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3288_uart1_fracmux
__initdata
=
MUX
(
SCLK_UART1
,
"sclk_uart1"
,
mux_uart1_p
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
14
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3288_uart2_fracmux
__initdata
=
MUX
(
SCLK_UART2
,
"sclk_uart2"
,
mux_uart2_p
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
15
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3288_uart3_fracmux
__initdata
=
MUX
(
SCLK_UART3
,
"sclk_uart3"
,
mux_uart3_p
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
16
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3288_uart4_fracmux
__initdata
=
MUX
(
SCLK_UART4
,
"sclk_uart4"
,
mux_uart4_p
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
3
),
8
,
2
,
MFLAGS
);
static
struct
rockchip_clk_branch
rk3288_clk_branches
[]
__initdata
=
{
static
struct
rockchip_clk_branch
rk3288_clk_branches
[]
__initdata
=
{
/*
/*
* Clock-Architecture Diagram 1
* Clock-Architecture Diagram 1
...
@@ -307,8 +339,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
...
@@ -307,8 +339,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"i2s_frac"
,
"i2s_src"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"i2s_frac"
,
"i2s_src"
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
8
),
0
,
RK3288_CLKSEL_CON
(
8
),
0
,
RK3288_CLKGATE_CON
(
4
),
2
,
GFLAGS
,
RK3288_CLKGATE_CON
(
4
),
2
,
GFLAGS
,
MUX
(
0
,
"i2s_pre"
,
mux_i2s_pre_p
,
CLK_SET_RATE_PARENT
,
&
rk3288_i2s_fracmux
),
RK3288_CLKSEL_CON
(
4
),
8
,
2
,
MFLAGS
)),
COMPOSITE_NODIV
(
SCLK_I2S0_OUT
,
"i2s0_clkout"
,
mux_i2s_clkout_p
,
0
,
COMPOSITE_NODIV
(
SCLK_I2S0_OUT
,
"i2s0_clkout"
,
mux_i2s_clkout_p
,
0
,
RK3288_CLKSEL_CON
(
4
),
12
,
1
,
MFLAGS
,
RK3288_CLKSEL_CON
(
4
),
12
,
1
,
MFLAGS
,
RK3288_CLKGATE_CON
(
4
),
0
,
GFLAGS
),
RK3288_CLKGATE_CON
(
4
),
0
,
GFLAGS
),
...
@@ -323,8 +354,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
...
@@ -323,8 +354,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"spdif_frac"
,
"spdif_src"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"spdif_frac"
,
"spdif_src"
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
9
),
0
,
RK3288_CLKSEL_CON
(
9
),
0
,
RK3288_CLKGATE_CON
(
4
),
5
,
GFLAGS
,
RK3288_CLKGATE_CON
(
4
),
5
,
GFLAGS
,
MUX
(
0
,
"spdif_mux"
,
mux_spdif_p
,
CLK_SET_RATE_PARENT
,
&
rk3288_spdif_fracmux
),
RK3288_CLKSEL_CON
(
5
),
8
,
2
,
MFLAGS
)),
GATE
(
SCLK_SPDIF
,
"sclk_spdif"
,
"spdif_mux"
,
CLK_SET_RATE_PARENT
,
GATE
(
SCLK_SPDIF
,
"sclk_spdif"
,
"spdif_mux"
,
CLK_SET_RATE_PARENT
,
RK3288_CLKGATE_CON
(
4
),
6
,
GFLAGS
),
RK3288_CLKGATE_CON
(
4
),
6
,
GFLAGS
),
COMPOSITE_NOMUX
(
0
,
"spdif_8ch_pre"
,
"spdif_src"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_NOMUX
(
0
,
"spdif_8ch_pre"
,
"spdif_src"
,
CLK_SET_RATE_PARENT
,
...
@@ -333,8 +363,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
...
@@ -333,8 +363,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"spdif_8ch_frac"
,
"spdif_8ch_pre"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"spdif_8ch_frac"
,
"spdif_8ch_pre"
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
41
),
0
,
RK3288_CLKSEL_CON
(
41
),
0
,
RK3288_CLKGATE_CON
(
4
),
8
,
GFLAGS
,
RK3288_CLKGATE_CON
(
4
),
8
,
GFLAGS
,
MUX
(
0
,
"spdif_8ch_mux"
,
mux_spdif_8ch_p
,
CLK_SET_RATE_PARENT
,
&
rk3288_spdif_8ch_fracmux
),
RK3288_CLKSEL_CON
(
40
),
8
,
2
,
MFLAGS
)),
GATE
(
SCLK_SPDIF8CH
,
"sclk_spdif_8ch"
,
"spdif_8ch_mux"
,
CLK_SET_RATE_PARENT
,
GATE
(
SCLK_SPDIF8CH
,
"sclk_spdif_8ch"
,
"spdif_8ch_mux"
,
CLK_SET_RATE_PARENT
,
RK3288_CLKGATE_CON
(
4
),
9
,
GFLAGS
),
RK3288_CLKGATE_CON
(
4
),
9
,
GFLAGS
),
...
@@ -541,8 +570,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
...
@@ -541,8 +570,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"uart0_frac"
,
"uart0_src"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"uart0_frac"
,
"uart0_src"
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
17
),
0
,
RK3288_CLKSEL_CON
(
17
),
0
,
RK3288_CLKGATE_CON
(
1
),
9
,
GFLAGS
,
RK3288_CLKGATE_CON
(
1
),
9
,
GFLAGS
,
MUX
(
SCLK_UART0
,
"sclk_uart0"
,
mux_uart0_p
,
CLK_SET_RATE_PARENT
,
&
rk3288_uart0_fracmux
),
RK3288_CLKSEL_CON
(
13
),
8
,
2
,
MFLAGS
)),
MUX
(
0
,
"uart_src"
,
mux_pll_src_cpll_gpll_p
,
0
,
MUX
(
0
,
"uart_src"
,
mux_pll_src_cpll_gpll_p
,
0
,
RK3288_CLKSEL_CON
(
13
),
15
,
1
,
MFLAGS
),
RK3288_CLKSEL_CON
(
13
),
15
,
1
,
MFLAGS
),
COMPOSITE_NOMUX
(
0
,
"uart1_src"
,
"uart_src"
,
0
,
COMPOSITE_NOMUX
(
0
,
"uart1_src"
,
"uart_src"
,
0
,
...
@@ -551,32 +579,28 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
...
@@ -551,32 +579,28 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_FRACMUX
(
0
,
"uart1_frac"
,
"uart1_src"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"uart1_frac"
,
"uart1_src"
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
18
),
0
,
RK3288_CLKSEL_CON
(
18
),
0
,
RK3288_CLKGATE_CON
(
1
),
11
,
GFLAGS
,
RK3288_CLKGATE_CON
(
1
),
11
,
GFLAGS
,
MUX
(
SCLK_UART1
,
"sclk_uart1"
,
mux_uart1_p
,
CLK_SET_RATE_PARENT
,
&
rk3288_uart1_fracmux
),
RK3288_CLKSEL_CON
(
14
),
8
,
2
,
MFLAGS
)),
COMPOSITE_NOMUX
(
0
,
"uart2_src"
,
"uart_src"
,
0
,
COMPOSITE_NOMUX
(
0
,
"uart2_src"
,
"uart_src"
,
0
,
RK3288_CLKSEL_CON
(
15
),
0
,
7
,
DFLAGS
,
RK3288_CLKSEL_CON
(
15
),
0
,
7
,
DFLAGS
,
RK3288_CLKGATE_CON
(
1
),
12
,
GFLAGS
),
RK3288_CLKGATE_CON
(
1
),
12
,
GFLAGS
),
COMPOSITE_FRACMUX
(
0
,
"uart2_frac"
,
"uart2_src"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"uart2_frac"
,
"uart2_src"
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
19
),
0
,
RK3288_CLKSEL_CON
(
19
),
0
,
RK3288_CLKGATE_CON
(
1
),
13
,
GFLAGS
,
RK3288_CLKGATE_CON
(
1
),
13
,
GFLAGS
,
MUX
(
SCLK_UART2
,
"sclk_uart2"
,
mux_uart2_p
,
CLK_SET_RATE_PARENT
,
&
rk3288_uart2_fracmux
),
RK3288_CLKSEL_CON
(
15
),
8
,
2
,
MFLAGS
)),
COMPOSITE_NOMUX
(
0
,
"uart3_src"
,
"uart_src"
,
0
,
COMPOSITE_NOMUX
(
0
,
"uart3_src"
,
"uart_src"
,
0
,
RK3288_CLKSEL_CON
(
16
),
0
,
7
,
DFLAGS
,
RK3288_CLKSEL_CON
(
16
),
0
,
7
,
DFLAGS
,
RK3288_CLKGATE_CON
(
1
),
14
,
GFLAGS
),
RK3288_CLKGATE_CON
(
1
),
14
,
GFLAGS
),
COMPOSITE_FRACMUX
(
0
,
"uart3_frac"
,
"uart3_src"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"uart3_frac"
,
"uart3_src"
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
20
),
0
,
RK3288_CLKSEL_CON
(
20
),
0
,
RK3288_CLKGATE_CON
(
1
),
15
,
GFLAGS
,
RK3288_CLKGATE_CON
(
1
),
15
,
GFLAGS
,
MUX
(
SCLK_UART3
,
"sclk_uart3"
,
mux_uart3_p
,
CLK_SET_RATE_PARENT
,
&
rk3288_uart3_fracmux
),
RK3288_CLKSEL_CON
(
16
),
8
,
2
,
MFLAGS
)),
COMPOSITE_NOMUX
(
0
,
"uart4_src"
,
"uart_src"
,
0
,
COMPOSITE_NOMUX
(
0
,
"uart4_src"
,
"uart_src"
,
0
,
RK3288_CLKSEL_CON
(
3
),
0
,
7
,
DFLAGS
,
RK3288_CLKSEL_CON
(
3
),
0
,
7
,
DFLAGS
,
RK3288_CLKGATE_CON
(
2
),
12
,
GFLAGS
),
RK3288_CLKGATE_CON
(
2
),
12
,
GFLAGS
),
COMPOSITE_FRACMUX
(
0
,
"uart4_frac"
,
"uart4_src"
,
CLK_SET_RATE_PARENT
,
COMPOSITE_FRACMUX
(
0
,
"uart4_frac"
,
"uart4_src"
,
CLK_SET_RATE_PARENT
,
RK3288_CLKSEL_CON
(
7
),
0
,
RK3288_CLKSEL_CON
(
7
),
0
,
RK3288_CLKGATE_CON
(
2
),
13
,
GFLAGS
,
RK3288_CLKGATE_CON
(
2
),
13
,
GFLAGS
,
MUX
(
SCLK_UART4
,
"sclk_uart4"
,
mux_uart4_p
,
CLK_SET_RATE_PARENT
,
&
rk3288_uart4_fracmux
),
RK3288_CLKSEL_CON
(
3
),
8
,
2
,
MFLAGS
)),
COMPOSITE
(
0
,
"mac_pll_src"
,
mux_pll_src_npll_cpll_gpll_p
,
0
,
COMPOSITE
(
0
,
"mac_pll_src"
,
mux_pll_src_npll_cpll_gpll_p
,
0
,
RK3288_CLKSEL_CON
(
21
),
0
,
2
,
MFLAGS
,
8
,
5
,
DFLAGS
,
RK3288_CLKSEL_CON
(
21
),
0
,
2
,
MFLAGS
,
8
,
5
,
DFLAGS
,
...
...
drivers/clk/rockchip/clk.h
View file @
49dea76a
...
@@ -424,7 +424,7 @@ struct rockchip_clk_branch {
...
@@ -424,7 +424,7 @@ struct rockchip_clk_branch {
.gate_offset = go, \
.gate_offset = go, \
.gate_shift = gs, \
.gate_shift = gs, \
.gate_flags = gf, \
.gate_flags = gf, \
.child =
&(struct rockchip_clk_branch)ch,
\
.child =
ch,
\
}
}
#define MUX(_id, cname, pnames, f, o, s, w, mf) \
#define MUX(_id, cname, pnames, f, o, s, w, mf) \
...
...
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