[ARM] Optimise io-writesl for cpus with ldr result delays.

arch/arm/lib/io-writesl.S

@@ -17,10 +17,15 @@ ENTRY(__raw_writesl)
 		ands	ip, r1, #3
 		bne	2f
 
-1:		ldr	r3, [r1], #4
-		str	r3, [r0]
-		subs	r2, r2, #1
-		bne	1b
+		tst	r2, #1
+		ldrne	r3, [r1], #4
+		strne	r3, [r0, #0]
+1:		subs	r2, r2, #2
+		ldrcs	r3, [r1], #4
+		ldrcs	ip, [r1], #4
+		strcs	r3, [r0, #0]
+		strcs	ip, [r0, #0]
+		bcs	1b
 		mov	pc, lr
 
 2:		bic	r1, r1, #3
@@ -31,25 +36,25 @@ ENTRY(__raw_writesl)
 
 3:		mov	ip, r3, lsr #16
 		ldr	r3, [r1], #4
-		orr	ip, ip, r3, lsl #16
-		str	ip, [r0]
 		subs	r2, r2, #1
+		orr	ip, ip, r3, lsl #16
+		str	ip, [r0, #0]
 		bne	3b
 		mov	pc, lr
 
 4:		mov	ip, r3, lsr #24
 		ldr	r3, [r1], #4
-		orr	ip, ip, r3, lsl #8
-		str	ip, [r0]
 		subs	r2, r2, #1
+		orr	ip, ip, r3, lsl #8
+		str	ip, [r0, #0]
 		bne	4b
 		mov	pc, lr
 
 5:		mov	ip, r3, lsr #8
 		ldr	r3, [r1], #4
-		orr	ip, ip, r3, lsl #24
-		str	ip, [r0]
 		subs	r2, r2, #1
+		orr	ip, ip, r3, lsl #24
+		str	ip, [r0, #0]
 		bne	5b
 		mov	pc, lr