Commit 4aa13243 authored by Loc Ho's avatar Loc Ho Committed by Greg Kroah-Hartman

clk: xgene: Fix divider with non-zero shift value

[ Upstream commit 1382ea63 ]

The X-Gene clock driver missed the divider shift operation when
set the divider value.
Signed-off-by: default avatarLoc Ho <lho@apm.com>
Fixes: 308964ca ("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarSasha Levin <alexander.levin@verizon.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c6210760
......@@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
/* Set new divider */
data = xgene_clk_read(pclk->param.divider_reg +
pclk->param.reg_divider_offset);
data &= ~((1 << pclk->param.reg_divider_width) - 1);
data &= ~((1 << pclk->param.reg_divider_width) - 1)
<< pclk->param.reg_divider_shift;
data |= divider;
xgene_clk_write(data, pclk->param.divider_reg +
pclk->param.reg_divider_offset);
......
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