Commit 4b60d29e authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter

agp/intel: map more registers for use by the GTT code

We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the
register for doing so is above the range we normally map.  Map the whole
register space to make sure we can get it.

v2: only map the larger space on gen7+ (Daniel)
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 90b107c8
...@@ -1206,12 +1206,16 @@ static inline int needs_idle_maps(void) ...@@ -1206,12 +1206,16 @@ static inline int needs_idle_maps(void)
static int i9xx_setup(void) static int i9xx_setup(void)
{ {
u32 reg_addr; u32 reg_addr;
int size = KB(512);
pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr); pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
reg_addr &= 0xfff80000; reg_addr &= 0xfff80000;
intel_private.registers = ioremap(reg_addr, 128 * 4096); if (INTEL_GTT_GEN >= 7)
size = MB(2);
intel_private.registers = ioremap(reg_addr, size);
if (!intel_private.registers) if (!intel_private.registers)
return -ENOMEM; return -ENOMEM;
......
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