Commit 4e1cbaa3 authored by Rob Clark's avatar Rob Clark

drm/msm: add chip-id param

Some of the w/a or different behavior of userspace blob driver seem to
be keyed to gpu patch revision, rather than gpu-id.  So expose the full
chip-id to userspace so it can DTRT.
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 37d77c3a
...@@ -73,6 +73,12 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) ...@@ -73,6 +73,12 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
case MSM_PARAM_GMEM_SIZE: case MSM_PARAM_GMEM_SIZE:
*value = adreno_gpu->gmem; *value = adreno_gpu->gmem;
return 0; return 0;
case MSM_PARAM_CHIP_ID:
*value = adreno_gpu->rev.patchid |
(adreno_gpu->rev.minor << 8) |
(adreno_gpu->rev.major << 16) |
(adreno_gpu->rev.core << 24);
return 0;
default: default:
DBG("%s: invalid param: %u", gpu->name, param); DBG("%s: invalid param: %u", gpu->name, param);
return -EINVAL; return -EINVAL;
......
...@@ -50,6 +50,7 @@ struct drm_msm_timespec { ...@@ -50,6 +50,7 @@ struct drm_msm_timespec {
#define MSM_PARAM_GPU_ID 0x01 #define MSM_PARAM_GPU_ID 0x01
#define MSM_PARAM_GMEM_SIZE 0x02 #define MSM_PARAM_GMEM_SIZE 0x02
#define MSM_PARAM_CHIP_ID 0x03
struct drm_msm_param { struct drm_msm_param {
uint32_t pipe; /* in, MSM_PIPE_x */ uint32_t pipe; /* in, MSM_PIPE_x */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment