Commit 4fa483e5 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher

drm/amd/powerplay: add raven support in smumgr. (v2)

smumgr provides the interface for interacting with the
smu firmware which handles power management.

v2: squash in updates (Alex)
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent adfc7f07
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef RAVEN_INC_H
#define RAVEN_INC_H
#include "asic_reg/raven1/MP/mp_10_0_default.h"
#include "asic_reg/raven1/MP/mp_10_0_offset.h"
#include "asic_reg/raven1/MP/mp_10_0_sh_mask.h"
#include "asic_reg/raven1/NBIO/nbio_7_0_default.h"
#include "asic_reg/raven1/NBIO/nbio_7_0_offset.h"
#include "asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h"
#include "asic_reg/raven1/THM/thm_10_0_default.h"
#include "asic_reg/raven1/THM/thm_10_0_offset.h"
#include "asic_reg/raven1/THM/thm_10_0_sh_mask.h"
#define ixDDI_PHY_GEN_STATUS 0x3FCE8
#endif
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef RAVEN_PP_SMC_H
#define RAVEN_PP_SMC_H
#pragma pack(push, 1)
#define PPSMC_Result_OK 0x1
#define PPSMC_Result_Failed 0xFF
#define PPSMC_Result_UnknownCmd 0xFE
#define PPSMC_Result_CmdRejectedPrereq 0xFD
#define PPSMC_Result_CmdRejectedBusy 0xFC
#define PPSMC_MSG_TestMessage 0x1
#define PPSMC_MSG_GetSmuVersion 0x2
#define PPSMC_MSG_GetDriverIfVersion 0x3
#define PPSMC_MSG_EnableGfxOff 0x7
#define PPSMC_MSG_DisableGfxOff 0x8
#define PPSMC_MSG_PowerDownIspByTile 0x9
#define PPSMC_MSG_PowerUpIspByTile 0xA
#define PPSMC_MSG_PowerDownVcn 0xB
#define PPSMC_MSG_PowerUpVcn 0xC
#define PPSMC_MSG_PowerDownSdma 0xD
#define PPSMC_MSG_PowerUpSdma 0xE
#define PPSMC_MSG_SetHardMinIspclkByFreq 0xF
#define PPSMC_MSG_SetHardMinVcn 0x10
#define PPSMC_MSG_SetMinDisplayClock 0x11
#define PPSMC_MSG_SetHardMinFclkByFreq 0x12
#define PPSMC_MSG_SetAllowFclkSwitch 0x13
#define PPSMC_MSG_SetGfxMinActiveFreq 0x14
#define PPSMC_MSG_ActiveProcessNotify 0x15
#define PPSMC_MSG_SetCustomPolicy 0x16
#define PPSMC_MSG_SetVideoFps 0x17
#define PPSMC_MSG_SetDisplayCount 0x18
#define PPSMC_MSG_QueryPowerLimit 0x19
#define PPSMC_MSG_SetDriverDramAddrHigh 0x1A
#define PPSMC_MSG_SetDriverDramAddrLow 0x1B
#define PPSMC_MSG_TransferTableSmu2Dram 0x1C
#define PPSMC_MSG_TransferTableDram2Smu 0x1D
#define PPSMC_MSG_ControlGfxRM 0x1E
#define PPSMC_MSG_SetGfxclkOverdriveByFreqVid 0x1F
#define PPSMC_MSG_SetHardMinDcefclkByFreq 0x20
#define PPSMC_MSG_SetHardMinSocclkByFreq 0x21
#define PPSMC_MSG_SetMinVddcrSocVoltage 0x22
#define PPSMC_Message_Count 0x23
typedef uint16_t PPSMC_Result;
typedef int PPSMC_Msg;
#pragma pack(pop)
#endif
...@@ -39,6 +39,7 @@ extern const struct pp_smumgr_func tonga_smu_funcs; ...@@ -39,6 +39,7 @@ extern const struct pp_smumgr_func tonga_smu_funcs;
extern const struct pp_smumgr_func fiji_smu_funcs; extern const struct pp_smumgr_func fiji_smu_funcs;
extern const struct pp_smumgr_func polaris10_smu_funcs; extern const struct pp_smumgr_func polaris10_smu_funcs;
extern const struct pp_smumgr_func vega10_smu_funcs; extern const struct pp_smumgr_func vega10_smu_funcs;
extern const struct pp_smumgr_func rv_smu_funcs;
enum AVFS_BTC_STATUS { enum AVFS_BTC_STATUS {
AVFS_BTC_BOOT = 0, AVFS_BTC_BOOT = 0,
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \ SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \
polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \ polaris10_smumgr.o iceland_smumgr.o polaris10_smc.o tonga_smc.o \
smu7_smumgr.o iceland_smc.o vega10_smumgr.o smu7_smumgr.o iceland_smc.o vega10_smumgr.o rv_smumgr.o
AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR)) AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
......
This diff is collapsed.
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef PP_RAVEN_SMUMANAGER_H
#define PP_RAVEN_SMUMANAGER_H
#include "rv_ppsmc.h"
#include "smu10_driver_if.h"
enum SMU_TABLE_ID {
WMTABLE = 0,
CLOCKTABLE,
MAX_SMU_TABLE,
};
struct smu_table_entry {
uint32_t version;
uint32_t size;
uint32_t table_id;
uint32_t table_addr_high;
uint32_t table_addr_low;
uint8_t *table;
uint32_t handle;
};
struct smu_table_array {
struct smu_table_entry entry[MAX_SMU_TABLE];
};
struct rv_smumgr {
struct smu_table_array smu_tables;
};
int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg);
bool rv_is_smc_ram_running(struct pp_smumgr *smumgr);
int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
uint8_t *table, int16_t table_id);
int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
uint8_t *table, int16_t table_id);
#endif
...@@ -95,6 +95,15 @@ int smum_early_init(struct pp_instance *handle) ...@@ -95,6 +95,15 @@ int smum_early_init(struct pp_instance *handle)
return -EINVAL; return -EINVAL;
} }
break; break;
case AMDGPU_FAMILY_RV:
switch (smumgr->chip_id) {
case CHIP_RAVEN:
smumgr->smumgr_funcs = &rv_smu_funcs;
break;
default:
return -EINVAL;
}
break;
default: default:
kfree(smumgr); kfree(smumgr);
return -EINVAL; return -EINVAL;
......
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