Commit 50166d1c authored by Prike.Liang's avatar Prike.Liang Committed by Alex Deucher

drm/amdgpu: enable HDP clock gatting

Enabe HDP SD/DS clock gatting in Renoir series.
Signed-off-by: default avatarPrike.Liang <Prike.Liang@amd.com>
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d844812b
...@@ -1452,7 +1452,8 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable ...@@ -1452,7 +1452,8 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable
uint32_t def, data; uint32_t def, data;
if (adev->asic_type == CHIP_VEGA20 || if (adev->asic_type == CHIP_VEGA20 ||
adev->asic_type == CHIP_ARCTURUS) { adev->asic_type == CHIP_ARCTURUS ||
adev->asic_type == CHIP_RENOIR) {
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
......
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