ARM: dts: sunxi: h3-h5: Move pinctrl of mmc0 from dts to dtsi

Most of the boards use the mmc0 pins and their attributes defined in
mmc0_pins_a. Let's default to those by moving the pinctrl attributes
to the dtsi file. This makes it easier to modify device trees in the
future as there is only one place to change the pinctrl attributes.
Signed-off-by: Joonas Kylmälä <joonas.kylmala@iki.fi>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts

@@ -60,8 +60,6 @@ &ehci0 {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	/*

arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts

@@ -112,8 +112,6 @@ &emac {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts

@@ -136,8 +136,6 @@ &ir {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm/boot/dts/sun8i-h3-beelink-x2.dts

@@ -115,8 +115,6 @@ &ir {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts

@@ -150,8 +150,6 @@ &ir {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc_io>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts

@@ -80,8 +80,6 @@ wifi_pwrseq: wifi_pwrseq {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm/boot/dts/sun8i-h3-nanopi.dtsi

@@ -96,8 +96,6 @@ &ehci3 {
 &mmc0 {
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	status = "okay";
 	vmmc-supply = <&reg_vcc3v3>;
 };

arch/arm/boot/dts/sun8i-h3-orangepi-2.dts

@@ -132,8 +132,6 @@ &ir {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts

@@ -106,8 +106,6 @@ &ir {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm/boot/dts/sun8i-h3-orangepi-one.dts

@@ -106,8 +106,6 @@ &emac {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts

@@ -128,8 +128,6 @@ &ir {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm/boot/dts/sunxi-h3-h5.dtsi

@@ -141,6 +141,8 @@ dma: dma-controller@1c02000 {
 		mmc0: mmc@1c0f000 {
 			/* compatible and clocks are in per SoC .dtsi file */
 			reg = <0x01c0f000 0x1000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins_a>;
 			resets = <&ccu RST_BUS_MMC0>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts

@@ -151,8 +151,6 @@ ext_rgmii_phy: ethernet-phy@7 {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts

@@ -126,8 +126,6 @@ ext_rgmii_phy: ethernet-phy@7 {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts

@@ -160,8 +160,6 @@ &ir {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts

@@ -167,8 +167,6 @@ &ir {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */

arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts

@@ -74,8 +74,6 @@ wifi_pwrseq: wifi_pwrseq {
 };
 
 &mmc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
 	bus-width = <4>;
 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;