Commit 511257e6 authored by Eric Engestrom's avatar Eric Engestrom Committed by Mauro Carvalho Chehab

[media] Documentation: dt: media: fix spelling mistake

Fix spelling mistake.
Signed-off-by: default avatarEric Engestrom <eric@engestrom.ch>
Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@osg.samsung.com>
parent 03567776
...@@ -20,7 +20,7 @@ The following properties are common to all Xilinx video IP cores. ...@@ -20,7 +20,7 @@ The following properties are common to all Xilinx video IP cores.
- xlnx,video-format: This property represents a video format transmitted on an - xlnx,video-format: This property represents a video format transmitted on an
AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
Video IP and System Design Guide" [UG934]. How the format relates to the IP Video IP and System Design Guide" [UG934]. How the format relates to the IP
core is decribed in the IP core bindings documentation. core is described in the IP core bindings documentation.
- xlnx,video-width: This property qualifies the video format with the sample - xlnx,video-width: This property qualifies the video format with the sample
width expressed as a number of bits per pixel component. All components must width expressed as a number of bits per pixel component. All components must
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