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Commit 547c32ae authored by Russell King's avatar Russell King Committed by Russell King
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Merge branch for-rmk-devel of git://aeryn.fluff.org.uk/bjdooks/linux into devel

parents b0efb424 99ae9953
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Showing with 4529 additions and 1358 deletions
Documentation/arm/Samsung-S3C24XX/GPIO.txt
View file @ 547c32ae
......@@ -51,7 +51,7 @@ PIN Numbers
-----------
Each pin has an unique number associated with it in regs-gpio.h,
eg S3C2410_GPA0 or S3C2410_GPF1. These defines are used to tell
eg S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell
the GPIO functions which pin is to be used.
......@@ -65,11 +65,11 @@ Configuring a pin
Eg:
s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
which would turn GPA0 into the lowest Address line A0, and set
GPE8 to be connected to the SDIO/MMC controller's SDDAT1 line.
which would turn GPA(0) into the lowest Address line A0, and set
GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line.
Reading the current configuration
......
arch/arm/common/Kconfig
View file @ 547c32ae
......@@ -4,6 +4,13 @@ config ARM_GIC
config ARM_VIC
bool
config ARM_VIC_NR
int
default 2
help
The maximum number of VICs available in the system, for
power management.
config ICST525
bool
......
arch/arm/common/vic.c
View file @ 547c32ae
......@@ -21,6 +21,7 @@
#include <linux/init.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <asm/mach/irq.h>
#include <asm/hardware/vic.h>
......@@ -39,11 +40,219 @@ static void vic_unmask_irq(unsigned int irq)
writel(1 << irq, base + VIC_INT_ENABLE);
}
/**
* vic_init2 - common initialisation code
* @base: Base of the VIC.
*
* Common initialisation code for registeration
* and resume.
*/
static void vic_init2(void __iomem *base)
{
int i;
for (i = 0; i < 16; i++) {
void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
writel(VIC_VECT_CNTL_ENABLE | i, reg);
}
writel(32, base + VIC_PL190_DEF_VECT_ADDR);
}
#if defined(CONFIG_PM)
/**
* struct vic_device - VIC PM device
* @sysdev: The system device which is registered.
* @irq: The IRQ number for the base of the VIC.
* @base: The register base for the VIC.
* @resume_sources: A bitmask of interrupts for resume.
* @resume_irqs: The IRQs enabled for resume.
* @int_select: Save for VIC_INT_SELECT.
* @int_enable: Save for VIC_INT_ENABLE.
* @soft_int: Save for VIC_INT_SOFT.
* @protect: Save for VIC_PROTECT.
*/
struct vic_device {
struct sys_device sysdev;
void __iomem *base;
int irq;
u32 resume_sources;
u32 resume_irqs;
u32 int_select;
u32 int_enable;
u32 soft_int;
u32 protect;
};
/* we cannot allocate memory when VICs are initially registered */
static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
static inline struct vic_device *to_vic(struct sys_device *sys)
{
return container_of(sys, struct vic_device, sysdev);
}
static int vic_id;
static int vic_class_resume(struct sys_device *dev)
{
struct vic_device *vic = to_vic(dev);
void __iomem *base = vic->base;
printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
/* re-initialise static settings */
vic_init2(base);
writel(vic->int_select, base + VIC_INT_SELECT);
writel(vic->protect, base + VIC_PROTECT);
/* set the enabled ints and then clear the non-enabled */
writel(vic->int_enable, base + VIC_INT_ENABLE);
writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
/* and the same for the soft-int register */
writel(vic->soft_int, base + VIC_INT_SOFT);
writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
return 0;
}
static int vic_class_suspend(struct sys_device *dev, pm_message_t state)
{
struct vic_device *vic = to_vic(dev);
void __iomem *base = vic->base;
printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
vic->int_select = readl(base + VIC_INT_SELECT);
vic->int_enable = readl(base + VIC_INT_ENABLE);
vic->soft_int = readl(base + VIC_INT_SOFT);
vic->protect = readl(base + VIC_PROTECT);
/* set the interrupts (if any) that are used for
* resuming the system */
writel(vic->resume_irqs, base + VIC_INT_ENABLE);
writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
return 0;
}
struct sysdev_class vic_class = {
.name = "vic",
.suspend = vic_class_suspend,
.resume = vic_class_resume,
};
/**
* vic_pm_register - Register a VIC for later power management control
* @base: The base address of the VIC.
* @irq: The base IRQ for the VIC.
* @resume_sources: bitmask of interrupts allowed for resume sources.
*
* Register the VIC with the system device tree so that it can be notified
* of suspend and resume requests and ensure that the correct actions are
* taken to re-instate the settings on resume.
*/
static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
{
struct vic_device *v;
if (vic_id >= ARRAY_SIZE(vic_devices))
printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
else {
v = &vic_devices[vic_id];
v->base = base;
v->resume_sources = resume_sources;
v->irq = irq;
vic_id++;
}
}
/**
* vic_pm_init - initicall to register VIC pm
*
* This is called via late_initcall() to register
* the resources for the VICs due to the early
* nature of the VIC's registration.
*/
static int __init vic_pm_init(void)
{
struct vic_device *dev = vic_devices;
int err;
int id;
if (vic_id == 0)
return 0;
err = sysdev_class_register(&vic_class);
if (err) {
printk(KERN_ERR "%s: cannot register class\n", __func__);
return err;
}
for (id = 0; id < vic_id; id++, dev++) {
dev->sysdev.id = id;
dev->sysdev.cls = &vic_class;
err = sysdev_register(&dev->sysdev);
if (err) {
printk(KERN_ERR "%s: failed to register device\n",
__func__);
return err;
}
}
return 0;
}
late_initcall(vic_pm_init);
static struct vic_device *vic_from_irq(unsigned int irq)
{
struct vic_device *v = vic_devices;
unsigned int base_irq = irq & ~31;
int id;
for (id = 0; id < vic_id; id++, v++) {
if (v->irq == base_irq)
return v;
}
return NULL;
}
static int vic_set_wake(unsigned int irq, unsigned int on)
{
struct vic_device *v = vic_from_irq(irq);
unsigned int off = irq & 31;
if (!v)
return -EINVAL;
if (on)
v->resume_irqs |= 1 << off;
else
v->resume_irqs &= ~(1 << off);
return 0;
}
#else
static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
#define vic_set_wake NULL
#endif /* CONFIG_PM */
static struct irq_chip vic_chip = {
.name = "VIC",
.ack = vic_mask_irq,
.mask = vic_mask_irq,
.unmask = vic_unmask_irq,
.set_wake = vic_set_wake,
};
/**
......@@ -51,9 +260,10 @@ static struct irq_chip vic_chip = {
* @base: iomem base address
* @irq_start: starting interrupt number, must be muliple of 32
* @vic_sources: bitmask of interrupt sources to allow
* @resume_sources: bitmask of interrupt sources to allow for resume
*/
void __init vic_init(void __iomem *base, unsigned int irq_start,
u32 vic_sources)
u32 vic_sources, u32 resume_sources)
{
unsigned int i;
......@@ -77,12 +287,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
writel(value, base + VIC_PL190_VECT_ADDR);
}
for (i = 0; i < 16; i++) {
void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
writel(VIC_VECT_CNTL_ENABLE | i, reg);
}
writel(32, base + VIC_PL190_DEF_VECT_ADDR);
vic_init2(base);
for (i = 0; i < 32; i++) {
if (vic_sources & (1 << i)) {
......@@ -94,4 +299,6 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
}
vic_pm_register(base, irq_start, resume_sources);
}
arch/arm/include/asm/hardware/pl080.h 0 → 100644
View file @ 547c32ae
/* arch/arm/include/asm/hardware/pl080.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* ARM PrimeCell PL080 DMA controller
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Note, there are some Samsung updates to this controller block which
* make it not entierly compatible with the PL080 specification from
* ARM. When in doubt, check the Samsung documentation first.
*
* The Samsung defines are PL080S, and add an extra controll register,
* the ability to move more than 2^11 counts of data and some extra
* OneNAND features.
*/
#define PL080_INT_STATUS (0x00)
#define PL080_TC_STATUS (0x04)
#define PL080_TC_CLEAR (0x08)
#define PL080_ERR_STATUS (0x0C)
#define PL080_ERR_CLEAR (0x10)
#define PL080_RAW_TC_STATUS (0x14)
#define PL080_RAW_ERR_STATUS (0x18)
#define PL080_EN_CHAN (0x1c)
#define PL080_SOFT_BREQ (0x20)
#define PL080_SOFT_SREQ (0x24)
#define PL080_SOFT_LBREQ (0x28)
#define PL080_SOFT_LSREQ (0x2C)
#define PL080_CONFIG (0x30)
#define PL080_CONFIG_M2_BE (1 << 2)
#define PL080_CONFIG_M1_BE (1 << 1)
#define PL080_CONFIG_ENABLE (1 << 0)
#define PL080_SYNC (0x34)
/* Per channel configuration registers */
#define PL008_Cx_STRIDE (0x20)
#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20)))
#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20)))
#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20)))
#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20)))
#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20)))
#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20)))
#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20)))
#define PL080_CH_SRC_ADDR (0x00)
#define PL080_CH_DST_ADDR (0x04)
#define PL080_CH_LLI (0x08)
#define PL080_CH_CONTROL (0x0C)
#define PL080_CH_CONFIG (0x10)
#define PL080S_CH_CONTROL2 (0x10)
#define PL080S_CH_CONFIG (0x14)
#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
#define PL080_LLI_ADDR_SHIFT (2)
#define PL080_LLI_LM_AHB2 (1 << 0)
#define PL080_CONTROL_TC_IRQ_EN (1 << 31)
#define PL080_CONTROL_PROT_MASK (0x7 << 28)
#define PL080_CONTROL_PROT_SHIFT (28)
#define PL080_CONTROL_PROT_SYS (1 << 28)
#define PL080_CONTROL_DST_INCR (1 << 27)
#define PL080_CONTROL_SRC_INCR (1 << 26)
#define PL080_CONTROL_DST_AHB2 (1 << 25)
#define PL080_CONTROL_SRC_AHB2 (1 << 24)
#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
#define PL080_CONTROL_DWIDTH_SHIFT (21)
#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
#define PL080_CONTROL_SWIDTH_SHIFT (18)
#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15)
#define PL080_CONTROL_DB_SIZE_SHIFT (15)
#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12)
#define PL080_CONTROL_SB_SIZE_SHIFT (12)
#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0)
#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
#define PL080_BSIZE_1 (0x0)
#define PL080_BSIZE_4 (0x1)
#define PL080_BSIZE_8 (0x2)
#define PL080_BSIZE_16 (0x3)
#define PL080_BSIZE_32 (0x4)
#define PL080_BSIZE_64 (0x5)
#define PL080_BSIZE_128 (0x6)
#define PL080_BSIZE_256 (0x7)
#define PL080_WIDTH_8BIT (0x0)
#define PL080_WIDTH_16BIT (0x1)
#define PL080_WIDTH_32BIT (0x2)
#define PL080_CONFIG_HALT (1 << 18)
#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */
#define PL080_CONFIG_LOCK (1 << 16)
#define PL080_CONFIG_TC_IRQ_MASK (1 << 15)
#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14)
#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
#define PL080_CONFIG_DST_SEL_SHIFT (6)
#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
#define PL080_CONFIG_SRC_SEL_SHIFT (1)
#define PL080_CONFIG_ENABLE (1 << 0)
#define PL080_FLOW_MEM2MEM (0x0)
#define PL080_FLOW_MEM2PER (0x1)
#define PL080_FLOW_PER2MEM (0x2)
#define PL080_FLOW_SRC2DST (0x3)
#define PL080_FLOW_SRC2DST_DST (0x4)
#define PL080_FLOW_MEM2PER_PER (0x5)
#define PL080_FLOW_PER2MEM_PER (0x6)
#define PL080_FLOW_SRC2DST_SRC (0x7)
/* DMA linked list chain structure */
struct pl080_lli {
u32 src_addr;
u32 dst_addr;
u32 next_lli;
u32 control0;
};
struct pl080s_lli {
u32 src_addr;
u32 dst_addr;
u32 next_lli;
u32 control0;
u32 control1;
};
arch/arm/include/asm/hardware/vic.h
View file @ 547c32ae
......@@ -41,7 +41,7 @@
#define VIC_PL192_VECT_ADDR 0xF00
#ifndef __ASSEMBLY__
void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources);
void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
#endif
#endif
arch/arm/mach-ep93xx/core.c
View file @ 547c32ae
......@@ -362,8 +362,8 @@ void __init ep93xx_init_irq(void)
{
int gpio_irq;
vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
for (gpio_irq = gpio_to_irq(0);
gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
......
arch/arm/mach-netx/generic.c
View file @ 547c32ae
......@@ -168,7 +168,7 @@ void __init netx_init_irq(void)
{
int irq;
vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0);
vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
set_irq_chip(irq, &netx_hif_chip);
......
arch/arm/mach-s3c2400/gpio.c
View file @ 547c32ae
......@@ -33,10 +33,10 @@
int s3c2400_gpio_getirq(unsigned int pin)
{
if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7)
return -1; /* not valid interrupts */
if (pin < S3C2410_GPE(0) || pin > S3C2400_GPE(7))
return -EINVAL; /* not valid interrupts */
return (pin - S3C2410_GPE0) + IRQ_EINT0;
return (pin - S3C2410_GPE(0)) + IRQ_EINT0;
}
EXPORT_SYMBOL(s3c2400_gpio_getirq);
arch/arm/mach-s3c2410/Kconfig
View file @ 547c32ae
......@@ -59,6 +59,7 @@ config ARCH_H1940
bool "IPAQ H1940"
select CPU_S3C2410
select PM_H1940 if PM
select S3C_DEV_USB_HOST
help
Say Y here if you are using the HP IPAQ H1940
......@@ -70,6 +71,7 @@ config PM_H1940
config MACH_N30
bool "Acer N30 family"
select CPU_S3C2410
select S3C_DEV_USB_HOST
help
Say Y here if you want suppt for the Acer N30, Acer N35,
Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
......@@ -82,6 +84,7 @@ config ARCH_BAST
select MACH_BAST_IDE
select S3C24XX_DCLK
select ISA
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Simtec Electronics EB2410ITX
development board (also known as BAST)
......@@ -89,6 +92,7 @@ config ARCH_BAST
config MACH_OTOM
bool "NexVision OTOM Board"
select CPU_S3C2410
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Nex Vision OTOM board
......@@ -96,6 +100,7 @@ config MACH_AML_M5900
bool "AML M5900 Series"
select CPU_S3C2410
select PM_SIMTEC if PM
select S3C_DEV_USB_HOST
help
Say Y here if you are using the American Microsystems M5900 Series
<http://www.amltd.com>
......@@ -111,6 +116,7 @@ config BAST_PC104_IRQ
config MACH_TCT_HAMMER
bool "TCT Hammer Board"
select CPU_S3C2410
select S3C_DEV_USB_HOST
help
Say Y here if you are using the TinCanTools Hammer Board
<http://www.tincantools.com>
......@@ -122,12 +128,14 @@ config MACH_VR1000
select SIMTEC_NOR
select MACH_BAST_IDE
select CPU_S3C2410
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Thorcom VR1000 board.
config MACH_QT2410
bool "QT2410"
select CPU_S3C2410
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Armzone QT2410
......
arch/arm/mach-s3c2410/dma.c
View file @ 547c32ae
......@@ -17,14 +17,16 @@
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <mach/map.h>
#include <mach/dma.h>
#include <plat/cpu.h>
#include <plat/dma.h>
#include <plat/dma-plat.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <plat/regs-ac97.h>
#include <plat/regs-dma.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
......
arch/arm/mach-s3c2410/gpio.c
View file @ 547c32ae
......@@ -39,12 +39,12 @@ int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
unsigned long flags;
unsigned long val;
if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
return -1;
if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15))
return -EINVAL;
config &= 0xff;
pin -= S3C2410_GPG8;
pin -= S3C2410_GPG(8);
reg += pin & ~3;
local_irq_save(flags);
......
arch/arm/mach-s3c2410/h1940-bluetooth.c
View file @ 547c32ae
......@@ -16,6 +16,8 @@
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <mach/regs-gpio.h>
#include <mach/hardware.h>
#include <mach/h1940-latch.h>
......@@ -41,9 +43,9 @@ static void h1940bt_enable(int on)
h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
/* Reset the chip */
mdelay(10);
s3c2410_gpio_setpin(S3C2410_GPH1, 1);
s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
mdelay(10);
s3c2410_gpio_setpin(S3C2410_GPH1, 0);
s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
state = 1;
}
......@@ -52,9 +54,9 @@ static void h1940bt_enable(int on)
led_trigger_event(bt_led_trigger, 0);
#endif
s3c2410_gpio_setpin(S3C2410_GPH1, 1);
s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
mdelay(10);
s3c2410_gpio_setpin(S3C2410_GPH1, 0);
s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
mdelay(10);
h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
......@@ -87,14 +89,14 @@ static DEVICE_ATTR(enable, 0644,
static int __init h1940bt_probe(struct platform_device *pdev)
{
/* Configures BT serial port GPIOs */
s3c2410_gpio_cfgpin(S3C2410_GPH0, S3C2410_GPH0_nCTS0);
s3c2410_gpio_pullup(S3C2410_GPH0, 1);
s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_OUTP);
s3c2410_gpio_pullup(S3C2410_GPH1, 1);
s3c2410_gpio_cfgpin(S3C2410_GPH2, S3C2410_GPH2_TXD0);
s3c2410_gpio_pullup(S3C2410_GPH2, 1);
s3c2410_gpio_cfgpin(S3C2410_GPH3, S3C2410_GPH3_RXD0);
s3c2410_gpio_pullup(S3C2410_GPH3, 1);
s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_pullup(S3C2410_GPH(1), 1);
s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
s3c2410_gpio_pullup(S3C2410_GPH(2), 1);
s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
s3c2410_gpio_pullup(S3C2410_GPH(3), 1);
#ifdef CONFIG_LEDS_H1940
led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger);
......
arch/arm/mach-s3c2410/include/mach/dma.h
View file @ 547c32ae
......@@ -3,7 +3,7 @@
* Copyright (C) 2003,2004,2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Samsung S3C241XX DMA support
* Samsung S3C24XX DMA support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
......@@ -13,8 +13,8 @@
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H __FILE__
#include <plat/dma.h>
#include <linux/sysdev.h>
#include <mach/hardware.h>
#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
......@@ -55,9 +55,9 @@ enum dma_ch {
/* we have 4 dma channels */
#ifndef CONFIG_CPU_S3C2443
#define S3C2410_DMA_CHANNELS (4)
#define S3C_DMA_CHANNELS (4)
#else
#define S3C2410_DMA_CHANNELS (6)
#define S3C_DMA_CHANNELS (6)
#endif
/* types */
......@@ -68,7 +68,6 @@ enum s3c2410_dma_state {
S3C2410_DMA_PAUSED
};
/* enum s3c2410_dma_loadst
*
* This represents the state of the DMA engine, wrt to the loaded / running
......@@ -104,32 +103,6 @@ enum s3c2410_dma_loadst {
S3C2410_DMALOAD_1LOADED_1RUNNING,
};
enum s3c2410_dma_buffresult {
S3C2410_RES_OK,
S3C2410_RES_ERR,
S3C2410_RES_ABORT
};
enum s3c2410_dmasrc {
S3C2410_DMASRC_HW, /* source is memory */
S3C2410_DMASRC_MEM /* source is hardware */
};
/* enum s3c2410_chan_op
*
* operation codes passed to the DMA code by the user, and also used
* to inform the current channel owner of any changes to the system state
*/
enum s3c2410_chan_op {
S3C2410_DMAOP_START,
S3C2410_DMAOP_STOP,
S3C2410_DMAOP_PAUSE,
S3C2410_DMAOP_RESUME,
S3C2410_DMAOP_FLUSH,
S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
S3C2410_DMAOP_STARTED, /* indicate channel started */
};
/* flags */
......@@ -139,17 +112,14 @@ enum s3c2410_chan_op {
/* dma buffer */
struct s3c2410_dma_client {
char *name;
};
struct s3c2410_dma_buf;
/* s3c2410_dma_buf_s
/* s3c2410_dma_buf
*
* internally used buffer structure to describe a queued or running
* buffer.
*/
struct s3c2410_dma_buf;
struct s3c2410_dma_buf {
struct s3c2410_dma_buf *next;
int magic; /* magic */
......@@ -161,20 +131,6 @@ struct s3c2410_dma_buf {
/* [1] is this updated for both recv/send modes? */
struct s3c2410_dma_chan;
/* s3c2410_dma_cbfn_t
*
* buffer callback routine type
*/
typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
void *buf, int size,
enum s3c2410_dma_buffresult result);
typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
enum s3c2410_chan_op );
struct s3c2410_dma_stats {
unsigned long loads;
unsigned long timeout_longest;
......@@ -206,10 +162,10 @@ struct s3c2410_dma_chan {
/* channel configuration */
enum s3c2410_dmasrc source;
enum dma_ch req_ch;
unsigned long dev_addr;
unsigned long load_timeout;
unsigned int flags; /* channel flags */
unsigned int hw_cfg; /* last hw config */
struct s3c24xx_dma_map *map; /* channel hw maps */
......@@ -236,213 +192,6 @@ struct s3c2410_dma_chan {
struct sys_device dev;
};
/* the currently allocated channel information */
extern struct s3c2410_dma_chan s3c2410_chans[];
/* note, we don't really use dma_device_t at the moment */
typedef unsigned long dma_device_t;
/* functions --------------------------------------------------------------- */
/* s3c2410_dma_request
*
* request a dma channel exclusivley
*/
extern int s3c2410_dma_request(unsigned int channel,
struct s3c2410_dma_client *, void *dev);
/* s3c2410_dma_ctrl
*
* change the state of the dma channel
*/
extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
/* s3c2410_dma_setflags
*
* set the channel's flags to a given state
*/
extern int s3c2410_dma_setflags(unsigned int channel,
unsigned int flags);
/* s3c2410_dma_free
*
* free the dma channel (will also abort any outstanding operations)
*/
extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
/* s3c2410_dma_enqueue
*
* place the given buffer onto the queue of operations for the channel.
* The buffer must be allocated from dma coherent memory, or the Dcache/WB
* drained before the buffer is given to the DMA system.
*/
extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
dma_addr_t data, int size);
/* s3c2410_dma_config
*
* configure the dma channel
*/
extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon);
/* s3c2410_dma_devconfig
*
* configure the device we're talking to
*/
extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
int hwcfg, unsigned long devaddr);
/* s3c2410_dma_getposition
*
* get the position that the dma transfer is currently at
*/
extern int s3c2410_dma_getposition(unsigned int channel,
dma_addr_t *src, dma_addr_t *dest);
extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
/* DMA Register definitions */
#define S3C2410_DMA_DISRC (0x00)
#define S3C2410_DMA_DISRCC (0x04)
#define S3C2410_DMA_DIDST (0x08)
#define S3C2410_DMA_DIDSTC (0x0C)
#define S3C2410_DMA_DCON (0x10)
#define S3C2410_DMA_DSTAT (0x14)
#define S3C2410_DMA_DCSRC (0x18)
#define S3C2410_DMA_DCDST (0x1C)
#define S3C2410_DMA_DMASKTRIG (0x20)
#define S3C2412_DMA_DMAREQSEL (0x24)
#define S3C2443_DMA_DMAREQSEL (0x24)
#define S3C2410_DISRCC_INC (1<<0)
#define S3C2410_DISRCC_APB (1<<1)
#define S3C2410_DMASKTRIG_STOP (1<<2)
#define S3C2410_DMASKTRIG_ON (1<<1)
#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
#define S3C2410_DCON_DEMAND (0<<31)
#define S3C2410_DCON_HANDSHAKE (1<<31)
#define S3C2410_DCON_SYNC_PCLK (0<<30)
#define S3C2410_DCON_SYNC_HCLK (1<<30)
#define S3C2410_DCON_INTREQ (1<<29)
#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
#define S3C2410_DCON_CH0_UART0 (1<<24)
#define S3C2410_DCON_CH0_SDI (2<<24)
#define S3C2410_DCON_CH0_TIMER (3<<24)
#define S3C2410_DCON_CH0_USBEP1 (4<<24)
#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
#define S3C2410_DCON_CH1_UART1 (1<<24)
#define S3C2410_DCON_CH1_I2SSDI (2<<24)
#define S3C2410_DCON_CH1_SPI (3<<24)
#define S3C2410_DCON_CH1_USBEP2 (4<<24)
#define S3C2410_DCON_CH2_I2SSDO (0<<24)
#define S3C2410_DCON_CH2_I2SSDI (1<<24)
#define S3C2410_DCON_CH2_SDI (2<<24)
#define S3C2410_DCON_CH2_TIMER (3<<24)
#define S3C2410_DCON_CH2_USBEP3 (4<<24)
#define S3C2410_DCON_CH3_UART2 (0<<24)
#define S3C2410_DCON_CH3_SDI (1<<24)
#define S3C2410_DCON_CH3_SPI (2<<24)
#define S3C2410_DCON_CH3_TIMER (3<<24)
#define S3C2410_DCON_CH3_USBEP4 (4<<24)
#define S3C2410_DCON_SRCSHIFT (24)
#define S3C2410_DCON_SRCMASK (7<<24)
#define S3C2410_DCON_BYTE (0<<20)
#define S3C2410_DCON_HALFWORD (1<<20)
#define S3C2410_DCON_WORD (2<<20)
#define S3C2410_DCON_AUTORELOAD (0<<22)
#define S3C2410_DCON_NORELOAD (1<<22)
#define S3C2410_DCON_HWTRIG (1<<23)
#ifdef CONFIG_CPU_S3C2440
#define S3C2440_DIDSTC_CHKINT (1<<2)
#define S3C2440_DCON_CH0_I2SSDO (5<<24)
#define S3C2440_DCON_CH0_PCMIN (6<<24)
#define S3C2440_DCON_CH1_PCMOUT (5<<24)
#define S3C2440_DCON_CH1_SDI (6<<24)
#define S3C2440_DCON_CH2_PCMIN (5<<24)
#define S3C2440_DCON_CH2_MICIN (6<<24)
#define S3C2440_DCON_CH3_MICIN (5<<24)
#define S3C2440_DCON_CH3_PCMOUT (6<<24)
#endif
#ifdef CONFIG_CPU_S3C2412
#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
#define S3C2412_DMAREQSEL_HW (1)
#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
#endif
#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
#define S3C2443_DMAREQSEL_HW (1)
#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
#endif /* __ASM_ARCH_DMA_H */
arch/arm/mach-s3c2410/include/mach/gpio-core.h
View file @ 547c32ae
......@@ -24,7 +24,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
{
struct s3c_gpio_chip *chip;
if (pin > S3C2410_GPG10)
if (pin > S3C2410_GPG(10))
return NULL;
chip = &s3c24xx_gpios[pin/32];
......
arch/arm/mach-s3c2410/include/mach/gpio-fns.h 0 → 100644
View file @ 547c32ae
/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
*
* Copyright (c) 2003,2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - hardware
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* These functions are in the to-be-removed category and it is strongly
* encouraged not to use these in new code. They will be marked deprecated
* very soon.
*
* Most of the functionality can be either replaced by the gpiocfg calls
* for the s3c platform or by the generic GPIOlib API.
*/
/* external functions for GPIO support
*
* These allow various different clients to access the same GPIO
* registers without conflicting. If your driver only owns the entire
* GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
*/
/* s3c2410_gpio_cfgpin
*
* set the configuration of the given pin to the value passed.
*
* eg:
* s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
* s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
*/
extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
/* s3c2410_gpio_getirq
*
* turn the given pin number into the corresponding IRQ number
*
* returns:
* < 0 = no interrupt for this pin
* >=0 = interrupt number for the pin
*/
extern int s3c2410_gpio_getirq(unsigned int pin);
#ifdef CONFIG_CPU_S3C2400
extern int s3c2400_gpio_getirq(unsigned int pin);
#endif /* CONFIG_CPU_S3C2400 */
/* s3c2410_gpio_irqfilter
*
* set the irq filtering on the given pin
*
* on = 0 => disable filtering
* 1 => enable filtering
*
* config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
* width of filter (0 through 63)
*
*
*/
extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
unsigned int config);
/* s3c2410_gpio_pullup
*
* configure the pull-up control on the given pin
*
* to = 1 => disable the pull-up
* 0 => enable the pull-up
*
* eg;
*
* s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
* s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
*/
extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
/* s3c2410_gpio_getpull
*
* Read the state of the pull-up on a given pin
*
* return:
* < 0 => error code
* 0 => enabled
* 1 => disabled
*/
extern int s3c2410_gpio_getpull(unsigned int pin);
extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
View file @ 547c32ae
......@@ -11,6 +11,9 @@
* published by the Free Software Foundation.
*/
#ifndef __MACH_GPIONRS_H
#define __MACH_GPIONRS_H
#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
#define S3C2410_GPIO_BANKA (32*0)
......@@ -21,3 +24,70 @@
#define S3C2410_GPIO_BANKF (32*5)
#define S3C2410_GPIO_BANKG (32*6)
#define S3C2410_GPIO_BANKH (32*7)
/* GPIO bank sizes */
#define S3C2410_GPIO_A_NR (32)
#define S3C2410_GPIO_B_NR (32)
#define S3C2410_GPIO_C_NR (32)
#define S3C2410_GPIO_D_NR (32)
#define S3C2410_GPIO_E_NR (32)
#define S3C2410_GPIO_F_NR (32)
#define S3C2410_GPIO_G_NR (32)
#define S3C2410_GPIO_H_NR (32)
#if CONFIG_S3C_GPIO_SPACE != 0
#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment
#endif
#define S3C2410_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
#ifndef __ASSEMBLY__
enum s3c_gpio_number {
S3C2410_GPIO_A_START = 0,
S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
};
#endif /* __ASSEMBLY__ */
/* S3C2410 GPIO number definitions. */
#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr))
#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr))
#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr))
#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr))
#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr))
#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
/* compatibility until drivers can be modified */
#define S3C2410_GPA0 S3C2410_GPA(0)
#define S3C2410_GPA1 S3C2410_GPA(1)
#define S3C2410_GPA3 S3C2410_GPA(3)
#define S3C2410_GPA7 S3C2410_GPA(7)
#define S3C2410_GPE0 S3C2410_GPE(0)
#define S3C2410_GPE1 S3C2410_GPE(1)
#define S3C2410_GPE2 S3C2410_GPE(2)
#define S3C2410_GPE3 S3C2410_GPE(3)
#define S3C2410_GPE4 S3C2410_GPE(4)
#define S3C2410_GPE5 S3C2410_GPE(5)
#define S3C2410_GPE6 S3C2410_GPE(6)
#define S3C2410_GPE7 S3C2410_GPE(7)
#define S3C2410_GPE8 S3C2410_GPE(8)
#define S3C2410_GPE9 S3C2410_GPE(9)
#define S3C2410_GPE10 S3C2410_GPE(10)
#define S3C2410_GPH10 S3C2410_GPH(10)
#endif /* __MACH_GPIONRS_H */
arch/arm/mach-s3c2410/include/mach/gpio.h
View file @ 547c32ae
......@@ -24,5 +24,6 @@
#include <asm-generic/gpio.h>
#include <mach/gpio-nrs.h>
#include <mach/gpio-fns.h>
#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
arch/arm/mach-s3c2410/include/mach/hardware.h
View file @ 547c32ae
......@@ -15,101 +15,6 @@
#ifndef __ASSEMBLY__
/* external functions for GPIO support
*
* These allow various different clients to access the same GPIO
* registers without conflicting. If your driver only owns the entire
* GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
*/
/* s3c2410_gpio_cfgpin
*
* set the configuration of the given pin to the value passed.
*
* eg:
* s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
* s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
*/
extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
/* s3c2410_gpio_getirq
*
* turn the given pin number into the corresponding IRQ number
*
* returns:
* < 0 = no interrupt for this pin
* >=0 = interrupt number for the pin
*/
extern int s3c2410_gpio_getirq(unsigned int pin);
/* s3c2410_gpio_irq2pin
*
* turn the given irq number into the corresponding GPIO number
*
* returns:
* < 0 = no pin
* >=0 = gpio pin number
*/
extern int s3c2410_gpio_irq2pin(unsigned int irq);
#ifdef CONFIG_CPU_S3C2400
extern int s3c2400_gpio_getirq(unsigned int pin);
#endif /* CONFIG_CPU_S3C2400 */
/* s3c2410_gpio_irqfilter
*
* set the irq filtering on the given pin
*
* on = 0 => disable filtering
* 1 => enable filtering
*
* config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
* width of filter (0 through 63)
*
*
*/
extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
unsigned int config);
/* s3c2410_gpio_pullup
*
* configure the pull-up control on the given pin
*
* to = 1 => disable the pull-up
* 0 => enable the pull-up
*
* eg;
*
* s3c2410_gpio_pullup(S3C2410_GPB0, 0);
* s3c2410_gpio_pullup(S3C2410_GPE8, 0);
*/
extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
/* s3c2410_gpio_getpull
*
* Read the state of the pull-up on a given pin
*
* return:
* < 0 => error code
* 0 => enabled
* 1 => disabled
*/
extern int s3c2410_gpio_getpull(unsigned int pin);
extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
#ifdef CONFIG_CPU_S3C2440
......
arch/arm/mach-s3c2410/include/mach/map.h
View file @ 547c32ae
......@@ -84,7 +84,6 @@
#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
#define S3C24XX_PA_DMA S3C2410_PA_DMA
#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
#define S3C24XX_PA_LCD S3C2410_PA_LCD
......@@ -102,6 +101,7 @@
#define S3C_PA_IIC S3C2410_PA_IIC
#define S3C_PA_UART S3C24XX_PA_UART
#define S3C_PA_USBHOST S3C2410_PA_USBHOST
#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
#endif /* __ASM_ARCH_MAP_H */
arch/arm/mach-s3c2410/include/mach/system-reset.h
View file @ 547c32ae
......@@ -11,21 +11,13 @@
*/
#include <mach/hardware.h>
#include <linux/io.h>
#include <plat/regs-watchdog.h>
#include <mach/regs-clock.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <plat/watchdog-reset.h>
extern void (*s3c24xx_reset_hook)(void);
static void
arch_reset(char mode, const char *cmd)
{
struct clk *wdtclk;
if (mode == 's') {
cpu_reset(0);
}
......@@ -33,31 +25,7 @@ arch_reset(char mode, const char *cmd)
if (s3c24xx_reset_hook)
s3c24xx_reset_hook();
printk("arch_reset: attempting watchdog reset\n");
__raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
wdtclk = clk_get(NULL, "watchdog");
if (!IS_ERR(wdtclk)) {
clk_enable(wdtclk);
} else
printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
/* put initial values into count and data */
__raw_writel(0x80, S3C2410_WTCNT);
__raw_writel(0x80, S3C2410_WTDAT);
/* set the watchdog to go and reset... */
__raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
/* wait for reset to assert... */
mdelay(500);
printk(KERN_ERR "Watchdog reset failed to assert reset\n");
/* delay to allow the serial port to show the message */
mdelay(50);
arch_wdt_reset();
/* we'll take a jump through zero as a poor second */
cpu_reset(0);
......
arch/arm/mach-s3c2410/mach-amlm5900.c
View file @ 547c32ae
......@@ -32,6 +32,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/proc_fs.h>
......@@ -224,8 +225,8 @@ static void amlm5900_init_pm(void)
} else {
enable_irq_wake(IRQ_EINT9);
/* configure the suspend/resume status pin */
s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP);
s3c2410_gpio_pullup(S3C2410_GPF2, 0);
s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_pullup(S3C2410_GPF(2), 0);
}
}
static void __init amlm5900_init(void)
......
arch/arm/mach-s3c2410/mach-bast.c
View file @ 547c32ae
......@@ -16,6 +16,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
......@@ -212,15 +213,15 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
{
/* ensure that an nRESET is not generated on resume. */
s3c2410_gpio_setpin(S3C2410_GPA21, 1);
s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
return 0;
}
static int bast_pm_resume(struct sys_device *sd)
{
s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
return 0;
}
......@@ -591,8 +592,6 @@ static void __init bast_map_io(void)
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
s3c24xx_init_clocks(0);
s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
usb_simtec_init();
}
static void __init bast_init(void)
......@@ -607,6 +606,7 @@ static void __init bast_init(void)
i2c_register_board_info(0, bast_i2c_devs,
ARRAY_SIZE(bast_i2c_devs));
usb_simtec_init();
nor_simtec_init();
}
......
arch/arm/mach-s3c2410/mach-h1940.c
View file @ 547c32ae
......@@ -127,7 +127,7 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = {
.udc_command = h1940_udc_pullup,
.vbus_pin = S3C2410_GPG5,
.vbus_pin = S3C2410_GPG(5),
.vbus_pin_inverted = 1,
};
......
arch/arm/mach-s3c2410/mach-n30.c
View file @ 547c32ae
......@@ -19,6 +19,7 @@
#include <linux/gpio_keys.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
......@@ -85,10 +86,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
{
switch (cmd) {
case S3C2410_UDC_P_ENABLE :
s3c2410_gpio_setpin(S3C2410_GPB3, 1);
s3c2410_gpio_setpin(S3C2410_GPB(3), 1);
break;
case S3C2410_UDC_P_DISABLE :
s3c2410_gpio_setpin(S3C2410_GPB3, 0);
s3c2410_gpio_setpin(S3C2410_GPB(3), 0);
break;
case S3C2410_UDC_P_RESET :
break;
......@@ -99,55 +100,55 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = {
.udc_command = n30_udc_pullup,
.vbus_pin = S3C2410_GPG1,
.vbus_pin = S3C2410_GPG(1),
.vbus_pin_inverted = 0,
};
static struct gpio_keys_button n30_buttons[] = {
{
.gpio = S3C2410_GPF0,
.gpio = S3C2410_GPF(0),
.code = KEY_POWER,
.desc = "Power",
.active_low = 0,
},
{
.gpio = S3C2410_GPG9,
.gpio = S3C2410_GPG(9),
.code = KEY_UP,
.desc = "Thumbwheel Up",
.active_low = 0,
},
{
.gpio = S3C2410_GPG8,
.gpio = S3C2410_GPG(8),
.code = KEY_DOWN,
.desc = "Thumbwheel Down",
.active_low = 0,
},
{
.gpio = S3C2410_GPG7,
.gpio = S3C2410_GPG(7),
.code = KEY_ENTER,
.desc = "Thumbwheel Press",
.active_low = 0,
},
{
.gpio = S3C2410_GPF7,
.gpio = S3C2410_GPF(7),
.code = KEY_HOMEPAGE,
.desc = "Home",
.active_low = 0,
},
{
.gpio = S3C2410_GPF6,
.gpio = S3C2410_GPF(6),
.code = KEY_CALENDAR,
.desc = "Calendar",
.active_low = 0,
},
{
.gpio = S3C2410_GPF5,
.gpio = S3C2410_GPF(5),
.code = KEY_ADDRESSBOOK,
.desc = "Contacts",
.active_low = 0,
},
{
.gpio = S3C2410_GPF4,
.gpio = S3C2410_GPF(4),
.code = KEY_MAIL,
.desc = "Mail",
.active_low = 0,
......@@ -169,73 +170,73 @@ static struct platform_device n30_button_device = {
static struct gpio_keys_button n35_buttons[] = {
{
.gpio = S3C2410_GPF0,
.gpio = S3C2410_GPF(0),
.code = KEY_POWER,
.desc = "Power",
.active_low = 0,
},
{
.gpio = S3C2410_GPG9,
.gpio = S3C2410_GPG(9),
.code = KEY_UP,
.desc = "Joystick Up",
.active_low = 0,
},
{
.gpio = S3C2410_GPG8,
.gpio = S3C2410_GPG(8),
.code = KEY_DOWN,
.desc = "Joystick Down",
.active_low = 0,
},
{
.gpio = S3C2410_GPG6,
.gpio = S3C2410_GPG(6),
.code = KEY_DOWN,
.desc = "Joystick Left",
.active_low = 0,
},
{
.gpio = S3C2410_GPG5,
.gpio = S3C2410_GPG(5),
.code = KEY_DOWN,
.desc = "Joystick Right",
.active_low = 0,
},
{
.gpio = S3C2410_GPG7,
.gpio = S3C2410_GPG(7),
.code = KEY_ENTER,
.desc = "Joystick Press",
.active_low = 0,
},
{
.gpio = S3C2410_GPF7,
.gpio = S3C2410_GPF(7),
.code = KEY_HOMEPAGE,
.desc = "Home",
.active_low = 0,
},
{
.gpio = S3C2410_GPF6,
.gpio = S3C2410_GPF(6),
.code = KEY_CALENDAR,
.desc = "Calendar",
.active_low = 0,
},
{
.gpio = S3C2410_GPF5,
.gpio = S3C2410_GPF(5),
.code = KEY_ADDRESSBOOK,
.desc = "Contacts",
.active_low = 0,
},
{
.gpio = S3C2410_GPF4,
.gpio = S3C2410_GPF(4),
.code = KEY_MAIL,
.desc = "Mail",
.active_low = 0,
},
{
.gpio = S3C2410_GPF3,
.gpio = S3C2410_GPF(3),
.code = SW_RADIO,
.desc = "GPS Antenna",
.active_low = 0,
},
{
.gpio = S3C2410_GPG2,
.gpio = S3C2410_GPG(2),
.code = SW_HEADPHONE_INSERT,
.desc = "Headphone",
.active_low = 0,
......@@ -259,7 +260,7 @@ static struct platform_device n35_button_device = {
/* This is the bluetooth LED on the device. */
static struct s3c24xx_led_platdata n30_blue_led_pdata = {
.name = "blue_led",
.gpio = S3C2410_GPG6,
.gpio = S3C2410_GPG(6),
.def_trigger = "",
};
......@@ -270,7 +271,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
static struct s3c24xx_led_platdata n30_warning_led_pdata = {
.name = "warning_led",
.flags = S3C24XX_LEDF_ACTLOW,
.gpio = S3C2410_GPD9,
.gpio = S3C2410_GPD(9),
.def_trigger = "",
};
......
arch/arm/mach-s3c2410/mach-qt2410.c
View file @ 547c32ae
......@@ -27,6 +27,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
......@@ -198,7 +199,7 @@ static struct platform_device qt2410_cs89x0 = {
/* LED */
static struct s3c24xx_led_platdata qt2410_pdata_led = {
.gpio = S3C2410_GPB0,
.gpio = S3C2410_GPB(0),
.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.name = "led",
.def_trigger = "timer",
......@@ -218,18 +219,18 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
{
switch (cs) {
case BITBANG_CS_ACTIVE:
s3c2410_gpio_setpin(S3C2410_GPB5, 0);
s3c2410_gpio_setpin(S3C2410_GPB(5), 0);
break;
case BITBANG_CS_INACTIVE:
s3c2410_gpio_setpin(S3C2410_GPB5, 1);
s3c2410_gpio_setpin(S3C2410_GPB(5), 1);
break;
}
}
static struct s3c2410_spigpio_info spi_gpio_cfg = {
.pin_clk = S3C2410_GPG7,
.pin_mosi = S3C2410_GPG6,
.pin_miso = S3C2410_GPG5,
.pin_clk = S3C2410_GPG(7),
.pin_mosi = S3C2410_GPG(6),
.pin_miso = S3C2410_GPG(5),
.chip_select = &spi_gpio_cs,
};
......@@ -346,13 +347,13 @@ static void __init qt2410_machine_init(void)
}
s3c24xx_fb_set_platdata(&qt2410_fb_info);
s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPB0, 1);
s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
s3c_i2c0_set_platdata(NULL);
s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT);
platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
s3c_pm_init();
......
arch/arm/mach-s3c2410/mach-vr1000.c
View file @ 547c32ae
......@@ -18,6 +18,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/dm9000.h>
#include <linux/i2c.h>
......@@ -277,19 +278,19 @@ static struct platform_device vr1000_dm9k1 = {
static struct s3c24xx_led_platdata vr1000_led1_pdata = {
.name = "led1",
.gpio = S3C2410_GPB0,
.gpio = S3C2410_GPB(0),
.def_trigger = "",
};
static struct s3c24xx_led_platdata vr1000_led2_pdata = {
.name = "led2",
.gpio = S3C2410_GPB1,
.gpio = S3C2410_GPB(1),
.def_trigger = "",
};
static struct s3c24xx_led_platdata vr1000_led3_pdata = {
.name = "led3",
.gpio = S3C2410_GPB2,
.gpio = S3C2410_GPB(2),
.def_trigger = "",
};
......@@ -355,8 +356,8 @@ static struct clk *vr1000_clocks[] __initdata = {
static void vr1000_power_off(void)
{
s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPB9_OUTP);
s3c2410_gpio_setpin(S3C2410_GPB9, 1);
s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPB(9), 1);
}
static void __init vr1000_map_io(void)
......
arch/arm/mach-s3c2410/pm.c
View file @ 547c32ae
......@@ -25,6 +25,7 @@
#include <linux/errno.h>
#include <linux/time.h>
#include <linux/sysdev.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <mach/hardware.h>
......@@ -76,7 +77,7 @@ static void s3c2410_pm_prepare(void)
}
if ( machine_is_aml_m5900() )
s3c2410_gpio_setpin(S3C2410_GPF2, 1);
s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
}
......@@ -91,7 +92,7 @@ static int s3c2410_pm_resume(struct sys_device *dev)
__raw_writel(tmp, S3C2410_GSTATUS2);
if ( machine_is_aml_m5900() )
s3c2410_gpio_setpin(S3C2410_GPF2, 0);
s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
return 0;
}
......
arch/arm/mach-s3c2410/usb-simtec.c
View file @ 547c32ae
......@@ -18,9 +18,11 @@
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/gpio.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <asm/mach/arch.h>
......@@ -29,7 +31,6 @@
#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include <mach/regs-gpio.h>
#include <mach/hardware.h>
#include <asm/irq.h>
......@@ -53,9 +54,9 @@ usb_simtec_powercontrol(int port, int to)
power_state[port] = to;
if (power_state[0] && power_state[1])
s3c2410_gpio_setpin(S3C2410_GPB4, 0);
gpio_set_value(S3C2410_GPB(4), 0);
else
s3c2410_gpio_setpin(S3C2410_GPB4, 1);
gpio_set_value(S3C2410_GPB(4), 1);
}
static irqreturn_t
......@@ -63,7 +64,7 @@ usb_simtec_ocirq(int irq, void *pw)
{
struct s3c2410_hcd_info *info = pw;
if (s3c2410_gpio_getpin(S3C2410_GPG10) == 0) {
if (gpio_get_value(S3C2410_GPG(10)) == 0) {
pr_debug("usb_simtec: over-current irq (oc detected)\n");
s3c2410_usb_report_oc(info, 3);
} else {
......@@ -106,10 +107,27 @@ static struct s3c2410_hcd_info usb_simtec_info = {
int usb_simtec_init(void)
{
int ret;
printk("USB Power Control, (c) 2004 Simtec Electronics\n");
s3c_device_usb.dev.platform_data = &usb_simtec_info;
s3c2410_gpio_cfgpin(S3C2410_GPB4, S3C2410_GPB4_OUTP);
s3c2410_gpio_setpin(S3C2410_GPB4, 1);
ret = gpio_request(S3C2410_GPB(4), "USB power control");
if (ret < 0) {
pr_err("%s: failed to get GPB4\n", __func__);
return ret;
}
ret = gpio_request(S3C2410_GPG(10), "USB overcurrent");
if (ret < 0) {
pr_err("%s: failed to get GPG10\n", __func__);
gpio_free(S3C2410_GPB(4));
return ret;
}
/* turn power on */
gpio_direction_output(S3C2410_GPB(4), 1);
gpio_direction_input(S3C2410_GPG(10));
s3c_device_usb.dev.platform_data = &usb_simtec_info;
return 0;
}
arch/arm/mach-s3c2412/Kconfig
View file @ 547c32ae
......@@ -38,6 +38,7 @@ menu "S3C2412 Machines"
config MACH_JIVE
bool "Logitech Jive"
select CPU_S3C2412
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Logitech Jive.
......@@ -50,6 +51,7 @@ config MACH_SMDK2413
select CPU_S3C2412
select MACH_S3C2413
select MACH_SMDK
select S3C_DEV_USB_HOST
help
Say Y here if you are using an SMDK2413
......@@ -72,6 +74,7 @@ config MACH_SMDK2412
config MACH_VSTMS
bool "VMSTMS"
select CPU_S3C2412
select S3C_DEV_USB_HOST
help
Say Y here if you are using an VSTMS board
......
arch/arm/mach-s3c2412/dma.c
View file @ 547c32ae
......@@ -20,12 +20,13 @@
#include <mach/dma.h>
#include <plat/dma.h>
#include <plat/dma-plat.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <plat/regs-ac97.h>
#include <plat/regs-dma.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
......
arch/arm/mach-s3c2412/mach-jive.c
View file @ 547c32ae
......@@ -16,6 +16,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
......@@ -356,8 +357,8 @@ static void jive_lcm_reset(unsigned int set)
{
printk(KERN_DEBUG "%s(%d)\n", __func__, set);
s3c2410_gpio_setpin(S3C2410_GPG13, set);
s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPG(13), set);
s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
}
#undef LCD_UPPER_MARGIN
......@@ -390,13 +391,13 @@ static struct ili9320_platdata jive_lcm_config = {
static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
{
s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
s3c2410_gpio_setpin(S3C2410_GPB(7), cs ? 0 : 1);
}
static struct s3c2410_spigpio_info jive_lcd_spi = {
.bus_num = 1,
.pin_clk = S3C2410_GPG8,
.pin_mosi = S3C2410_GPB8,
.pin_clk = S3C2410_GPG(8),
.pin_mosi = S3C2410_GPB(8),
.num_chipselect = 1,
.chip_select = jive_lcd_spi_chipselect,
};
......@@ -412,13 +413,13 @@ static struct platform_device jive_device_lcdspi = {
static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
{
s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1);
s3c2410_gpio_setpin(S3C2410_GPH(10), cs ? 0 : 1);
}
static struct s3c2410_spigpio_info jive_wm8750_spi = {
.bus_num = 2,
.pin_clk = S3C2410_GPB4,
.pin_mosi = S3C2410_GPB9,
.pin_clk = S3C2410_GPB(4),
.pin_mosi = S3C2410_GPB(9),
.num_chipselect = 1,
.chip_select = jive_wm8750_chipselect,
};
......@@ -479,7 +480,7 @@ static struct platform_device *jive_devices[] __initdata = {
};
static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
.vbus_pin = S3C2410_GPG1, /* detect is on GPG1 */
.vbus_pin = S3C2410_GPG(1), /* detect is on GPG1 */
};
/* Jive power management device */
......@@ -529,8 +530,8 @@ static void jive_power_off(void)
{
printk(KERN_INFO "powering system down...\n");
s3c2410_gpio_setpin(S3C2410_GPC5, 1);
s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
}
static void __init jive_machine_init(void)
......@@ -634,22 +635,22 @@ static void __init jive_machine_init(void)
/* initialise the spi */
s3c2410_gpio_setpin(S3C2410_GPG13, 0);
s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPG(13), 0);
s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPB7, 1);
s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPB(7), 1);
s3c2410_gpio_cfgpin(S3C2410_GPB(7), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPB6, 0);
s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
s3c2410_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPG8, 1);
s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
s3c2410_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
/* initialise the WM8750 spi */
s3c2410_gpio_setpin(S3C2410_GPH10, 1);
s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPH(10), 1);
s3c2410_gpio_cfgpin(S3C2410_GPH(10), S3C2410_GPIO_OUTPUT);
/* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */
......
arch/arm/mach-s3c2412/mach-smdk2413.c
View file @ 547c32ae
......@@ -17,6 +17,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
......@@ -84,10 +85,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd)
switch (cmd)
{
case S3C2410_UDC_P_ENABLE :
s3c2410_gpio_setpin(S3C2410_GPF2, 1);
s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
break;
case S3C2410_UDC_P_DISABLE :
s3c2410_gpio_setpin(S3C2410_GPF2, 0);
s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
break;
case S3C2410_UDC_P_RESET :
break;
......@@ -134,8 +135,8 @@ static void __init smdk2413_machine_init(void)
{ /* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */
s3c2410_gpio_setpin(S3C2410_GPF2, 0);
s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
S3C2410_MISCCR_USBSUSPND0 |
......
arch/arm/mach-s3c2440/Kconfig
View file @ 547c32ae
......@@ -33,6 +33,7 @@ config MACH_ANUBIS
select PM_SIMTEC if PM
select HAVE_PATA_PLATFORM
select S3C24XX_GPIO_EXTRA64
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Simtec Electronics ANUBIS
development system
......@@ -43,6 +44,7 @@ config MACH_OSIRIS
select S3C24XX_DCLK
select PM_SIMTEC if PM
select S3C24XX_GPIO_EXTRA128
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Simtec IM2440D20 module, also
known as the Osiris.
......@@ -58,12 +60,14 @@ config ARCH_S3C2440
bool "SMDK2440"
select CPU_S3C2440
select MACH_SMDK
select S3C_DEV_USB_HOST
help
Say Y here if you are using the SMDK2440.
config MACH_NEXCODER_2440
bool "NexVision NEXCODER 2440 Light Board"
select CPU_S3C2440
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
......@@ -76,6 +80,7 @@ config SMDK2440_CPU2440
config MACH_AT2440EVB
bool "Avantech AT2440EVB development board"
select CPU_S3C2440
select S3C_DEV_USB_HOST
help
Say Y here if you are using the AT2440EVB development board
......
arch/arm/mach-s3c2440/dma.c
View file @ 547c32ae
......@@ -17,14 +17,16 @@
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <mach/map.h>
#include <mach/dma.h>
#include <plat/dma.h>
#include <plat/dma-plat.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <plat/regs-ac97.h>
#include <plat/regs-dma.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
......
arch/arm/mach-s3c2440/mach-anubis.c
View file @ 547c32ae
......@@ -15,6 +15,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
......@@ -468,7 +469,7 @@ static void __init anubis_map_io(void)
anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
} else {
/* ensure that the GPIO is setup */
s3c2410_gpio_setpin(S3C2410_GPA0, 1);
s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
}
}
......
arch/arm/mach-s3c2440/mach-at2440evb.c
View file @ 547c32ae
......@@ -166,7 +166,7 @@ static struct platform_device at2440evb_device_eth = {
};
static struct s3c24xx_mci_pdata at2440evb_mci_pdata = {
.gpio_detect = S3C2410_GPG10,
.gpio_detect = S3C2410_GPG(10),
};
/* 7" LCD panel */
......
arch/arm/mach-s3c2440/mach-nexcoder.c
View file @ 547c32ae
......@@ -18,6 +18,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/string.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
......@@ -120,16 +121,16 @@ static struct platform_device *nexcoder_devices[] __initdata = {
static void __init nexcoder_sensorboard_init(void)
{
// Initialize SCCB bus
s3c2410_gpio_setpin(S3C2410_GPE14, 1); // IICSCL
s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_OUTP);
s3c2410_gpio_setpin(S3C2410_GPE15, 1); // IICSDA
s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_OUTP);
s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
// Power up the sensor board
s3c2410_gpio_setpin(S3C2410_GPF1, 1);
s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_OUTP); // CAM_GPIO7 => nLDO_PWRDN
s3c2410_gpio_setpin(S3C2410_GPF2, 0);
s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); // CAM_GPIO6 => CAM_PWRDN
s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
s3c2410_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
}
static void __init nexcoder_map_io(void)
......
arch/arm/mach-s3c2440/mach-osiris.c
View file @ 547c32ae
......@@ -15,6 +15,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
......@@ -291,8 +292,8 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
__raw_writeb(tmp, OSIRIS_VA_CTRL0);
/* ensure that an nRESET is not generated on resume. */
s3c2410_gpio_setpin(S3C2410_GPA21, 1);
s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
return 0;
}
......@@ -304,7 +305,7 @@ static int osiris_pm_resume(struct sys_device *sd)
__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
return 0;
}
......@@ -384,7 +385,7 @@ static void __init osiris_map_io(void)
osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
} else {
/* write-protect line to the NAND */
s3c2410_gpio_setpin(S3C2410_GPA0, 1);
s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
}
/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
......
arch/arm/mach-s3c2443/dma.c
View file @ 547c32ae
......@@ -20,12 +20,13 @@
#include <mach/dma.h>
#include <plat/dma.h>
#include <plat/dma-plat.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <plat/regs-ac97.h>
#include <plat/regs-dma.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
......
arch/arm/mach-s3c6400/Kconfig
View file @ 547c32ae
......@@ -5,4 +5,27 @@
#
# Licensed under GPLv2
# Currently nothing here, this will be added later
# Configuration options for the S3C6410 CPU
config CPU_S3C6400
bool
select CPU_S3C6400_INIT
select CPU_S3C6400_CLOCK
help
Enable S3C6400 CPU support
config S3C6400_SETUP_SDHCI
bool
help
Internal configuration for default SDHCI
setup for S3C6400.
# S36400 Macchine support
config MACH_SMDK6400
bool "SMDK6400"
select CPU_S3C6400
select S3C_DEV_HSMMC
select S3C6400_SETUP_SDHCI
help
Machine support for the Samsung SMDK6400
arch/arm/mach-s3c6400/Makefile
View file @ 547c32ae
......@@ -12,4 +12,12 @@ obj- :=
# Core support for S3C6400 system
obj-n += blank.o
obj-$(CONFIG_CPU_S3C6400) += s3c6400.o
# setup support
obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci.o
# Machine support
obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
arch/arm/mach-s3c6400/include/mach/dma.h
View file @ 547c32ae
......@@ -11,6 +11,63 @@
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H __FILE__
/* currently nothing here, placeholder */
#define S3C_DMA_CHANNELS (16)
/* see mach-s3c2410/dma.h for notes on dma channel numbers */
/* Note, for the S3C64XX architecture we keep the DMACH_
* defines in the order they are allocated to [S]DMA0/[S]DMA1
* so that is easy to do DHACH_ -> DMA controller conversion
*/
enum dma_ch {
/* DMA0/SDMA0 */
DMACH_UART0 = 0,
DMACH_UART0_SRC2,
DMACH_UART1,
DMACH_UART1_SRC2,
DMACH_UART2,
DMACH_UART2_SRC2,
DMACH_UART3,
DMACH_UART3_SRC2,
DMACH_PCM0_TX,
DMACH_PCM0_RX,
DMACH_I2S0_OUT,
DMACH_I2S0_IN,
DMACH_SPI0_TX,
DMACH_SPI0_RX,
DMACH_HSI_I2SV40_TX,
DMACH_HSI_I2SV40_RX,
/* DMA1/SDMA1 */
DMACH_PCM1_TX = 16,
DMACH_PCM1_RX,
DMACH_I2S1_OUT,
DMACH_I2S1_IN,
DMACH_SPI1_TX,
DMACH_SPI1_RX,
DMACH_AC97_PCMOUT,
DMACH_AC97_PCMIN,
DMACH_AC97_MICIN,
DMACH_PWM,
DMACH_IRDA,
DMACH_EXTERNAL,
DMACH_RES1,
DMACH_RES2,
DMACH_SECURITY_RX, /* SDMA1 only */
DMACH_SECURITY_TX, /* SDMA1 only */
DMACH_MAX /* the end */
};
static __inline__ int s3c_dma_has_circular(void)
{
/* we will be supporting ciruclar buffers as soon as we have DMA
* engine support.
*/
return 1;
}
#define S3C2410_DMAF_CIRCULAR (1 << 0)
#include <plat/dma.h>
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s3c6400/include/mach/map.h
View file @ 547c32ae
......@@ -39,6 +39,8 @@
#define S3C_VA_UART3 S3C_VA_UARTx(3)
#define S3C64XX_PA_FB (0x77100000)
#define S3C64XX_PA_USB_HSOTG (0x7C000000)
#define S3C64XX_PA_WATCHDOG (0x7E004000)
#define S3C64XX_PA_SYSCON (0x7E00F000)
#define S3C64XX_PA_IIS0 (0x7F002000)
#define S3C64XX_PA_IIS1 (0x7F003000)
......@@ -57,6 +59,8 @@
#define S3C64XX_PA_MODEM (0x74108000)
#define S3C64XX_VA_MODEM S3C_ADDR(0x00600000)
#define S3C64XX_PA_USBHOST (0x74300000)
/* place VICs close together */
#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00)
#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
......@@ -69,5 +73,7 @@
#define S3C_PA_IIC S3C64XX_PA_IIC0
#define S3C_PA_IIC1 S3C64XX_PA_IIC1
#define S3C_PA_FB S3C64XX_PA_FB
#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
#endif /* __ASM_ARCH_6400_MAP_H */
arch/arm/mach-s3c6400/include/mach/regs-clock.h 0 → 100644
View file @ 547c32ae
/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - clock register compatibility with s3c24xx
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <plat/regs-clock.h>
arch/arm/mach-s3c6400/include/mach/system.h
View file @ 547c32ae
......@@ -11,6 +11,8 @@
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H __FILE__
#include <plat/watchdog-reset.h>
static void arch_idle(void)
{
/* nothing here yet */
......@@ -18,7 +20,11 @@ static void arch_idle(void)
static void arch_reset(char mode, const char *cmd)
{
/* nothing here yet */
if (mode != 's')
arch_wdt_reset();
/* if all else fails, or mode was for soft, jump to 0 */
cpu_reset(0);
}
#endif /* __ASM_ARCH_IRQ_H */
arch/arm/mach-s3c6400/mach-smdk6400.c 0 → 100644
View file @ 547c32ae
/* linux/arch/arm/mach-s3c6400/mach-smdk6400.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/regs-serial.h>
#include <plat/s3c6400.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/iic.h>
#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
static struct s3c2410_uartcfg smdk6400_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
};
static struct map_desc smdk6400_iodesc[] = {};
static void __init smdk6400_map_io(void)
{
s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
}
static struct platform_device *smdk6400_devices[] __initdata = {
&s3c_device_hsmmc1,
&s3c_device_i2c0,
};
static struct i2c_board_info i2c_devs[] __initdata = {
{ I2C_BOARD_INFO("wm8753", 0x1A), },
{ I2C_BOARD_INFO("24c08", 0x50), },
};
static void __init smdk6400_machine_init(void)
{
i2c_register_board_info(0, i2c_devs, ARRAY_SIZE(i2c_devs));
platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices));
}
MACHINE_START(SMDK6400, "SMDK6400")
/* Maintainer: Ben Dooks <ben@fluff.org> */
.phys_io = S3C_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C64XX_PA_SDRAM + 0x100,
.init_irq = s3c6400_init_irq,
.map_io = smdk6400_map_io,
.init_machine = smdk6400_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END
arch/arm/mach-s3c6400/s3c6400.c 0 → 100644
View file @ 547c32ae
/* linux/arch/arm/mach-s3c6410/cpu.c
*
* Copyright 2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <plat/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/sdhci.h>
#include <plat/iic-core.h>
#include <plat/s3c6400.h>
void __init s3c6400_map_io(void)
{
/* setup SDHCI */
s3c6400_default_sdhci0();
s3c6400_default_sdhci1();
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
}
void __init s3c6400_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s3c64xx_register_clocks();
s3c6400_register_clocks(S3C6400_CLKDIV0_ARM_MASK);
s3c6400_setup_clocks();
}
void __init s3c6400_init_irq(void)
{
/* VIC0 does not have IRQS 5..7,
* VIC1 is fully populated. */
s3c64xx_init_irq(~0 & ~(0xf << 5), ~0);
}
struct sysdev_class s3c6400_sysclass = {
.name = "s3c6400-core",
};
static struct sys_device s3c6400_sysdev = {
.cls = &s3c6400_sysclass,
};
static int __init s3c6400_core_init(void)
{
return sysdev_class_register(&s3c6400_sysclass);
}
core_initcall(s3c6400_core_init);
int __init s3c6400_init(void)
{
printk("S3C6400: Initialising architecture\n");
return sysdev_register(&s3c6400_sysdev);
}
arch/arm/mach-s3c6400/setup-sdhci.c 0 → 100644
View file @ 547c32ae
/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
*
* Copyright 2008 Simtec Electronics
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
char *s3c6400_hsmmc_clksrcs[4] = {
[0] = "hsmmc",
[1] = "hsmmc",
[2] = "mmc_bus",
/* [3] = "48m", - note not succesfully used yet */
};
void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card)
{
u32 ctrl2, ctrl3;
ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
S3C_SDHCI_CTRL2_ENFBCLKRX |
S3C_SDHCI_CTRL2_DFCNT_NONE |
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
if (ios->clock < 25 * 1000000)
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
S3C_SDHCI_CTRL3_FCSEL2 |
S3C_SDHCI_CTRL3_FCSEL1 |
S3C_SDHCI_CTRL3_FCSEL0);
else
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}
arch/arm/mach-s3c6410/Kconfig
View file @ 547c32ae
......@@ -16,9 +16,18 @@ config CPU_S3C6410
config S3C6410_SETUP_SDHCI
bool
select S3C64XX_SETUP_SDHCI_GPIO
help
Internal helper functions for S3C6410 based SDHCI systems
config MACH_ANW6410
bool "A&W6410"
select CPU_S3C6410
select S3C_DEV_FB
select S3C64XX_SETUP_FB_24BPP
help
Machine support for the A&W6410
config MACH_SMDK6410
bool "SMDK6410"
select CPU_S3C6410
......@@ -26,6 +35,8 @@ config MACH_SMDK6410
select S3C_DEV_HSMMC1
select S3C_DEV_I2C1
select S3C_DEV_FB
select S3C_DEV_USB_HOST
select S3C_DEV_USB_HSOTG
select S3C6410_SETUP_SDHCI
select S3C64XX_SETUP_I2C1
select S3C64XX_SETUP_FB_24BPP
......@@ -60,3 +71,29 @@ config SMDK6410_SD_CH1
channels 0 and 1 are the same.
endchoice
config SMDK6410_WM1190_EV1
bool "Support Wolfson Microelectronics 1190-EV1 PMIC card"
depends on MACH_SMDK6410
select REGULATOR
select REGULATOR_WM8350
select MFD_WM8350_I2C
select MFD_WM8350_CONFIG_MODE_0
select MFD_WM8350_CONFIG_MODE_3
select MFD_WM8352_CONFIG_MODE_0
help
The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC
and audio daughtercard for the Samsung SMDK6410 reference
platform. Enabling this option will build support for this
module into the kernel. The presence of the module will be
detected at runtime so the the resulting kernel can be used
with or without the 1190-EV1 fitted.
config MACH_NCP
bool "NCP"
select CPU_S3C6410
select S3C_DEV_I2C1
select S3C_DEV_HSMMC1
select S3C64XX_SETUP_I2C1
help
Machine support for the Samsung NCP
arch/arm/mach-s3c6410/Makefile
View file @ 547c32ae
......@@ -20,4 +20,8 @@ obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o
# machine support
obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
obj-$(CONFIG_MACH_NCP) += mach-ncp.o
arch/arm/mach-s3c6410/cpu.c
View file @ 547c32ae
......@@ -31,6 +31,7 @@
#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <plat/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
......@@ -68,7 +69,7 @@ void __init s3c6410_init_clocks(int xtal)
printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s3c64xx_register_clocks();
s3c6400_register_clocks();
s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK);
s3c6400_setup_clocks();
}
......
arch/arm/mach-s3c6410/mach-anw6410.c 0 → 100644
View file @ 547c32ae
/* linux/arch/arm/mach-s3c6410/mach-anw6410.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
* Copyright 2009 Kwangwoo Lee
* Kwangwoo Lee <kwangwoo.lee@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/dm9000.h>
#include <video/platform_lcd.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/regs-fb.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/regs-gpio.h>
#include <plat/regs-modem.h>
/* DM9000 */
#define ANW6410_PA_DM9000 (0x18000000)
/* A hardware buffer to control external devices is mapped at 0x30000000.
* It can not be read. So current status must be kept in anw6410_extdev_status.
*/
#define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000)
#define ANW6410_PA_EXTDEV (0x30000000)
#define ANW6410_EN_DM9000 (1<<11)
#define ANW6410_EN_LCD (1<<14)
static __u32 anw6410_extdev_status;
static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
};
/* framebuffer and LCD setup. */
static void __init anw6410_lcd_mode_set(void)
{
u32 tmp;
/* set the LCD type */
tmp = __raw_readl(S3C64XX_SPCON);
tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
__raw_writel(tmp, S3C64XX_SPCON);
/* remove the LCD bypass */
tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
tmp &= ~MIFPCON_LCD_BYPASS;
__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
}
/* GPF1 = LCD panel power
* GPF4 = LCD backlight control
*/
static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
if (power) {
anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
gpio_direction_output(S3C64XX_GPF(1), 1);
gpio_direction_output(S3C64XX_GPF(4), 1);
} else {
anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
gpio_direction_output(S3C64XX_GPF(1), 0);
gpio_direction_output(S3C64XX_GPF(4), 0);
}
}
static struct plat_lcd_data anw6410_lcd_power_data = {
.set_power = anw6410_lcd_power_set,
};
static struct platform_device anw6410_lcd_powerdev = {
.name = "platform-lcd",
.dev.parent = &s3c_device_fb.dev,
.dev.platform_data = &anw6410_lcd_power_data,
};
static struct s3c_fb_pd_win anw6410_fb_win0 = {
/* this is to ensure we use win0 */
.win_mode = {
.pixclock = 41094,
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 16,
};
/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
.win[0] = &anw6410_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
/* DM9000AEP 10/100 ethernet controller */
static void __init anw6410_dm9000_enable(void)
{
anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
}
static struct resource anw6410_dm9000_resource[] = {
[0] = {
.start = ANW6410_PA_DM9000,
.end = ANW6410_PA_DM9000 + 3,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = ANW6410_PA_DM9000 + 4,
.end = ANW6410_PA_DM9000 + 4 + 500,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = IRQ_EINT(15),
.end = IRQ_EINT(15),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
},
};
static struct dm9000_plat_data anw6410_dm9000_pdata = {
.flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
/* dev_addr can be set to provide hwaddr. */
};
static struct platform_device anw6410_device_eth = {
.name = "dm9000",
.id = -1,
.num_resources = ARRAY_SIZE(anw6410_dm9000_resource),
.resource = anw6410_dm9000_resource,
.dev = {
.platform_data = &anw6410_dm9000_pdata,
},
};
static struct map_desc anw6410_iodesc[] __initdata = {
{
.virtual = (unsigned long)ANW6410_VA_EXTDEV,
.pfn = __phys_to_pfn(ANW6410_PA_EXTDEV),
.length = SZ_64K,
.type = MT_DEVICE,
},
};
static struct platform_device *anw6410_devices[] __initdata = {
&s3c_device_fb,
&anw6410_lcd_powerdev,
&anw6410_device_eth,
};
static void __init anw6410_map_io(void)
{
s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
anw6410_lcd_mode_set();
}
static void __init anw6410_machine_init(void)
{
s3c_fb_set_platdata(&anw6410_lcd_pdata);
gpio_request(S3C64XX_GPF(1), "panel power");
gpio_request(S3C64XX_GPF(4), "LCD backlight");
anw6410_dm9000_enable();
platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
}
MACHINE_START(ANW6410, "A&W6410")
/* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
.phys_io = S3C_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C64XX_PA_SDRAM + 0x100,
.init_irq = s3c6410_init_irq,
.map_io = anw6410_map_io,
.init_machine = anw6410_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END
arch/arm/mach-s3c6410/mach-ncp.c 0 → 100644
View file @ 547c32ae
/*
* linux/arch/arm/mach-s3c6410/mach-ncp.c
*
* Copyright (C) 2008-2009 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <video/platform_lcd.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/regs-fb.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#define UCON S3C2410_UCON_DEFAULT
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
static struct s3c2410_uartcfg ncp_uartcfgs[] __initdata = {
/* REVISIT: NCP uses only serial 1, 2 */
[0] = {
.hwport = 0,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
};
static struct platform_device *ncp_devices[] __initdata = {
&s3c_device_hsmmc1,
&s3c_device_i2c0,
};
struct map_desc ncp_iodesc[] = {};
static void __init ncp_map_io(void)
{
s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
}
static void __init ncp_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(ncp_devices, ARRAY_SIZE(ncp_devices));
}
MACHINE_START(NCP, "NCP")
/* Maintainer: Samsung Electronics */
.phys_io = S3C_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C64XX_PA_SDRAM + 0x100,
.init_irq = s3c6410_init_irq,
.map_io = ncp_map_io,
.init_machine = ncp_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END
arch/arm/mach-s3c6410/mach-smdk6410.c
View file @ 547c32ae
......@@ -24,6 +24,12 @@
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/smsc911x.h>
#ifdef CONFIG_SMDK6410_WM1190_EV1
#include <linux/mfd/wm8350/core.h>
#include <linux/mfd/wm8350/pmic.h>
#endif
#include <video/platform_lcd.h>
......@@ -39,8 +45,12 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/regs-modem.h>
#include <plat/regs-gpio.h>
#include <plat/regs-sys.h>
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
#include <plat/s3c6410.h>
#include <plat/clock.h>
......@@ -129,6 +139,37 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
static struct resource smdk6410_smsc911x_resources[] = {
[0] = {
.start = 0x18000000,
.end = 0x18000000 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = S3C_EINT(10),
.end = S3C_EINT(10),
.flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
},
};
static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
.phy_interface = PHY_INTERFACE_MODE_MII,
};
static struct platform_device smdk6410_smsc911x = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
.resource = &smdk6410_smsc911x_resources[0],
.dev = {
.platform_data = &smdk6410_smsc911x_pdata,
},
};
static struct map_desc smdk6410_iodesc[] = {};
static struct platform_device *smdk6410_devices[] __initdata = {
......@@ -141,12 +182,155 @@ static struct platform_device *smdk6410_devices[] __initdata = {
&s3c_device_i2c0,
&s3c_device_i2c1,
&s3c_device_fb,
&s3c_device_usb,
&s3c_device_usb_hsotg,
&smdk6410_lcd_powerdev,
&smdk6410_smsc911x,
};
#ifdef CONFIG_SMDK6410_WM1190_EV1
/* S3C64xx internal logic & PLL */
static struct regulator_init_data wm8350_dcdc1_data = {
.constraints = {
.name = "PVDD_INT/PVDD_PLL",
.min_uV = 1200000,
.max_uV = 1200000,
.always_on = 1,
.apply_uV = 1,
},
};
/* Memory */
static struct regulator_init_data wm8350_dcdc3_data = {
.constraints = {
.name = "PVDD_MEM",
.min_uV = 1800000,
.max_uV = 1800000,
.always_on = 1,
.state_mem = {
.uV = 1800000,
.mode = REGULATOR_MODE_NORMAL,
.enabled = 1,
},
.initial_state = PM_SUSPEND_MEM,
},
};
/* USB, EXT, PCM, ADC/DAC, USB, MMC */
static struct regulator_init_data wm8350_dcdc4_data = {
.constraints = {
.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
.min_uV = 3000000,
.max_uV = 3000000,
.always_on = 1,
},
};
/* ARM core */
static struct regulator_consumer_supply dcdc6_consumers[] = {
{
.supply = "vddarm",
}
};
static struct regulator_init_data wm8350_dcdc6_data = {
.constraints = {
.name = "PVDD_ARM",
.min_uV = 1000000,
.max_uV = 1300000,
.always_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
.consumer_supplies = dcdc6_consumers,
};
/* Alive */
static struct regulator_init_data wm8350_ldo1_data = {
.constraints = {
.name = "PVDD_ALIVE",
.min_uV = 1200000,
.max_uV = 1200000,
.always_on = 1,
.apply_uV = 1,
},
};
/* OTG */
static struct regulator_init_data wm8350_ldo2_data = {
.constraints = {
.name = "PVDD_OTG",
.min_uV = 3300000,
.max_uV = 3300000,
.always_on = 1,
},
};
/* LCD */
static struct regulator_init_data wm8350_ldo3_data = {
.constraints = {
.name = "PVDD_LCD",
.min_uV = 3000000,
.max_uV = 3000000,
.always_on = 1,
},
};
/* OTGi/1190-EV1 HPVDD & AVDD */
static struct regulator_init_data wm8350_ldo4_data = {
.constraints = {
.name = "PVDD_OTGI/HPVDD/AVDD",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.always_on = 1,
},
};
static struct {
int regulator;
struct regulator_init_data *initdata;
} wm1190_regulators[] = {
{ WM8350_DCDC_1, &wm8350_dcdc1_data },
{ WM8350_DCDC_3, &wm8350_dcdc3_data },
{ WM8350_DCDC_4, &wm8350_dcdc4_data },
{ WM8350_DCDC_6, &wm8350_dcdc6_data },
{ WM8350_LDO_1, &wm8350_ldo1_data },
{ WM8350_LDO_2, &wm8350_ldo2_data },
{ WM8350_LDO_3, &wm8350_ldo3_data },
{ WM8350_LDO_4, &wm8350_ldo4_data },
};
static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
{
int i;
/* Instantiate the regulators */
for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
wm8350_register_regulator(wm8350,
wm1190_regulators[i].regulator,
wm1190_regulators[i].initdata);
return 0;
}
static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
.init = smdk6410_wm8350_init,
.irq_high = 1,
};
#endif
static struct i2c_board_info i2c_devs0[] __initdata = {
{ I2C_BOARD_INFO("24c08", 0x50), },
{ I2C_BOARD_INFO("wm8580", 0x1b), },
#ifdef CONFIG_SMDK6410_WM1190_EV1
{ I2C_BOARD_INFO("wm8350", 0x1a),
.platform_data = &smdk6410_wm8350_pdata,
.irq = S3C_EINT(12),
},
#endif
};
static struct i2c_board_info i2c_devs1[] __initdata = {
......@@ -155,9 +339,23 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
static void __init smdk6410_map_io(void)
{
u32 tmp;
s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
/* set the LCD type */
tmp = __raw_readl(S3C64XX_SPCON);
tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
__raw_writel(tmp, S3C64XX_SPCON);
/* remove the lcd bypass */
tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
tmp &= ~MIFPCON_LCD_BYPASS;
__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
}
static void __init smdk6410_machine_init(void)
......
arch/arm/mach-s3c6410/setup-sdhci.c
View file @ 547c32ae
......@@ -21,8 +21,6 @@
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <mach/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
......@@ -35,22 +33,6 @@ char *s3c6410_hsmmc_clksrcs[4] = {
/* [3] = "48m", - note not succesfully used yet */
};
void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
end = S3C64XX_GPG(2 + width);
/* Set all the necessary GPG pins to special-function 0 */
for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
}
void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
void __iomem *r,
......@@ -84,19 +66,3 @@ void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}
void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
end = S3C64XX_GPH(2 + width);
/* Set all the necessary GPG pins to special-function 0 */
for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
}
arch/arm/mach-versatile/core.c
View file @ 547c32ae
......@@ -116,7 +116,7 @@ void __init versatile_init_irq(void)
{
unsigned int i;
vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
......
arch/arm/plat-s3c/Kconfig
View file @ 547c32ae
......@@ -71,6 +71,15 @@ config S3C2410_PM_DEBUG
Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
for more information.
config S3C_PM_DEBUG_LED_SMDK
bool "SMDK LED suspend/resume debugging"
depends on PM && (MACH_SMDK6410)
help
Say Y here to enable the use of the SMDK LEDs on the baseboard
for debugging of the state of the suspend and resume process.
Note, this currently only works for S3C64XX based SMDK boards.
config S3C2410_PM_CHECK
bool "S3C2410 PM Suspend Memory CRC"
depends on PM && CRC32
......@@ -150,6 +159,13 @@ config S3C_GPIO_CFG_S3C64XX
Internal configuration to enable S3C64XX style GPIO configuration
functions.
# DMA
config S3C_DMA
bool
help
Internal configuration for S3C DMA core
# device definitions to compile in
config S3C_DEV_HSMMC
......@@ -172,4 +188,14 @@ config S3C_DEV_FB
help
Compile in platform device definition for framebuffer
config S3C_DEV_USB_HOST
bool
help
Compile in platform device definition for USB host.
config S3C_DEV_USB_HSOTG
bool
help
Compile in platform device definition for USB high-speed OtG
endif
arch/arm/plat-s3c/Makefile
View file @ 547c32ae
......@@ -18,9 +18,14 @@ obj-y += pwm-clock.o
obj-y += gpio.o
obj-y += gpio-config.o
# DMA support
obj-$(CONFIG_S3C_DMA) += dma.o
# PM support
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM) += pm-gpio.o
obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o
# devices
......@@ -30,3 +35,5 @@ obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
obj-y += dev-i2c0.o
obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o
obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
arch/arm/plat-s3c/dev-usb-hsotg.c 0 → 100644
View file @ 547c32ae
/* linux/arch/arm/plat-s3c/dev-usb-hsotg.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for USB high-speed UDC/OtG block
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <mach/irqs.h>
#include <mach/map.h>
#include <plat/devs.h>
static struct resource s3c_usb_hsotg_resources[] = {
[0] = {
.start = S3C_PA_USB_HSOTG,
.end = S3C_PA_USB_HSOTG + 0x10000 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_OTG,
.end = IRQ_OTG,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_usb_hsotg = {
.name = "s3c-hsotg",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
.resource = s3c_usb_hsotg_resources,
};
arch/arm/plat-s3c/dev-usb.c 0 → 100644
View file @ 547c32ae
/* linux/arch/arm/plat-s3c/dev-usb.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for USB host
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <mach/irqs.h>
#include <mach/map.h>
#include <plat/devs.h>
static struct resource s3c_usb_resource[] = {
[0] = {
.start = S3C_PA_USBHOST,
.end = S3C_PA_USBHOST + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_USBH,
.end = IRQ_USBH,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_usb_dmamask = 0xffffffffUL;
struct platform_device s3c_device_usb = {
.name = "s3c2410-ohci",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_usb_resource),
.resource = s3c_usb_resource,
.dev = {
.dma_mask = &s3c_device_usb_dmamask,
.coherent_dma_mask = 0xffffffffUL
}
};
EXPORT_SYMBOL(s3c_device_usb);
arch/arm/plat-s3c/dma.c 0 → 100644
View file @ 547c32ae
/* linux/arch/arm/plat-s3c/dma.c
*
* Copyright (c) 2003-2005,2006,2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C DMA core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
struct s3c2410_dma_buf;
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <mach/dma.h>
#include <mach/irqs.h>
#include <plat/dma-plat.h>
/* dma channel state information */
struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
/* s3c_dma_lookup_channel
*
* change the dma channel number given into a real dma channel id
*/
struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
{
if (channel & DMACH_LOW_LEVEL)
return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
else
return s3c_dma_chan_map[channel];
}
/* do we need to protect the settings of the fields from
* irq?
*/
int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
{
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
if (chan == NULL)
return -EINVAL;
pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
chan->op_fn = rtn;
return 0;
}
EXPORT_SYMBOL(s3c2410_dma_set_opfn);
int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
{
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
if (chan == NULL)
return -EINVAL;
pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
chan->callback_fn = rtn;
return 0;
}
EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
{
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
if (chan == NULL)
return -EINVAL;
chan->flags = flags;
return 0;
}
EXPORT_SYMBOL(s3c2410_dma_setflags);
arch/arm/plat-s3c/gpio.c
View file @ 547c32ae
......@@ -16,7 +16,7 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <plat/gpio-core.h>
#include <mach/gpio-core.h>
#ifdef CONFIG_S3C_GPIO_TRACK
struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
......@@ -140,6 +140,15 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
if (!gc->get)
gc->get = s3c_gpiolib_get;
#ifdef CONFIG_PM
if (chip->pm != NULL) {
if (!chip->pm->save || !chip->pm->resume)
printk(KERN_ERR "gpio: %s has missing PM functions\n",
gc->label);
} else
printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
#endif
/* gpiochip_add() prints own failure message on error. */
ret = gpiochip_add(gc);
if (ret >= 0)
......
arch/arm/plat-s3c/include/plat/adc.h
View file @ 547c32ae
......@@ -19,10 +19,12 @@ struct s3c_adc_client;
extern int s3c_adc_start(struct s3c_adc_client *client,
unsigned int channel, unsigned int nr_samples);
extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
void (*select)(unsigned selected),
void (*conv)(unsigned d0, unsigned d1),
unsigned int is_ts);
extern struct s3c_adc_client *
s3c_adc_register(struct platform_device *pdev,
void (*select)(unsigned selected),
void (*conv)(unsigned d0, unsigned d1,
unsigned *samples_left),
unsigned int is_ts);
extern void s3c_adc_release(struct s3c_adc_client *client);
......
arch/arm/plat-s3c/include/plat/clock.h
View file @ 547c32ae
......@@ -50,6 +50,7 @@ extern struct clk clk_xtal;
extern struct clk clk_ext;
/* S3C64XX specific clocks */
extern struct clk clk_h2;
extern struct clk clk_27m;
extern struct clk clk_48m;
......
arch/arm/plat-s3c/include/plat/cpu.h
View file @ 547c32ae
......@@ -69,3 +69,6 @@ extern struct sysdev_class s3c2412_sysclass;
extern struct sysdev_class s3c2440_sysclass;
extern struct sysdev_class s3c2442_sysclass;
extern struct sysdev_class s3c2443_sysclass;
extern struct sysdev_class s3c6410_sysclass;
extern struct sysdev_class s3c64xx_sysclass;
arch/arm/plat-s3c/include/plat/devs.h
View file @ 547c32ae
......@@ -45,6 +45,7 @@ extern struct platform_device s3c_device_spi1;
extern struct platform_device s3c_device_nand;
extern struct platform_device s3c_device_usbgadget;
extern struct platform_device s3c_device_usb_hsotg;
/* s3c2440 specific devices */
......
arch/arm/plat-s3c/include/plat/dma-core.h 0 → 100644
View file @ 547c32ae
/* arch/arm/plat-s3c/include/plat/dma.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Samsung S3C DMA core support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
/* the currently allocated channel information */
extern struct s3c2410_dma_chan s3c2410_chans[];
arch/arm/plat-s3c/include/plat/dma.h 0 → 100644
View file @ 547c32ae
/* arch/arm/plat-s3c/include/plat/dma.h
*
* Copyright (C) 2003,2004,2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Samsung S3C DMA support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
enum s3c2410_dma_buffresult {
S3C2410_RES_OK,
S3C2410_RES_ERR,
S3C2410_RES_ABORT
};
enum s3c2410_dmasrc {
S3C2410_DMASRC_HW, /* source is memory */
S3C2410_DMASRC_MEM /* source is hardware */
};
/* enum s3c2410_chan_op
*
* operation codes passed to the DMA code by the user, and also used
* to inform the current channel owner of any changes to the system state
*/
enum s3c2410_chan_op {
S3C2410_DMAOP_START,
S3C2410_DMAOP_STOP,
S3C2410_DMAOP_PAUSE,
S3C2410_DMAOP_RESUME,
S3C2410_DMAOP_FLUSH,
S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
S3C2410_DMAOP_STARTED, /* indicate channel started */
};
struct s3c2410_dma_client {
char *name;
};
struct s3c2410_dma_chan;
/* s3c2410_dma_cbfn_t
*
* buffer callback routine type
*/
typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
void *buf, int size,
enum s3c2410_dma_buffresult result);
typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
enum s3c2410_chan_op );
/* s3c2410_dma_request
*
* request a dma channel exclusivley
*/
extern int s3c2410_dma_request(unsigned int channel,
struct s3c2410_dma_client *, void *dev);
/* s3c2410_dma_ctrl
*
* change the state of the dma channel
*/
extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
/* s3c2410_dma_setflags
*
* set the channel's flags to a given state
*/
extern int s3c2410_dma_setflags(unsigned int channel,
unsigned int flags);
/* s3c2410_dma_free
*
* free the dma channel (will also abort any outstanding operations)
*/
extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
/* s3c2410_dma_enqueue
*
* place the given buffer onto the queue of operations for the channel.
* The buffer must be allocated from dma coherent memory, or the Dcache/WB
* drained before the buffer is given to the DMA system.
*/
extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
dma_addr_t data, int size);
/* s3c2410_dma_config
*
* configure the dma channel
*/
extern int s3c2410_dma_config(unsigned int channel, int xferunit);
/* s3c2410_dma_devconfig
*
* configure the device we're talking to
*/
extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
unsigned long devaddr);
/* s3c2410_dma_getposition
*
* get the position that the dma transfer is currently at
*/
extern int s3c2410_dma_getposition(unsigned int channel,
dma_addr_t *src, dma_addr_t *dest);
extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
arch/arm/plat-s3c/include/plat/gpio-core.h
View file @ 547c32ae
......@@ -20,6 +20,18 @@
* specific code.
*/
struct s3c_gpio_chip;
/**
* struct s3c_gpio_pm - power management (suspend/resume) information
* @save: Routine to save the state of the GPIO block
* @resume: Routine to resume the GPIO block.
*/
struct s3c_gpio_pm {
void (*save)(struct s3c_gpio_chip *chip);
void (*resume)(struct s3c_gpio_chip *chip);
};
struct s3c_gpio_cfg;
/**
......@@ -27,6 +39,7 @@ struct s3c_gpio_cfg;
* @chip: The chip structure to be exported via gpiolib.
* @base: The base pointer to the gpio configuration registers.
* @config: special function and pull-resistor control information.
* @pm_save: Save information for suspend/resume support.
*
* This wrapper provides the necessary information for the Samsung
* specific gpios being registered with gpiolib.
......@@ -34,7 +47,11 @@ struct s3c_gpio_cfg;
struct s3c_gpio_chip {
struct gpio_chip chip;
struct s3c_gpio_cfg *config;
struct s3c_gpio_pm *pm;
void __iomem *base;
#ifdef CONFIG_PM
u32 pm_save[4];
#endif
};
static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
......@@ -75,3 +92,16 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
#endif
#ifdef CONFIG_PM
extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
#define __gpio_pm(x) x
#else
#define s3c_gpio_pm_1bit NULL
#define s3c_gpio_pm_2bit NULL
#define s3c_gpio_pm_4bit NULL
#define __gpio_pm(x) NULL
#endif /* CONFIG_PM */
arch/arm/plat-s3c/include/plat/pm.h
View file @ 547c32ae
......@@ -44,6 +44,8 @@ extern void (*pm_cpu_sleep)(void);
extern unsigned long s3c_pm_flags;
extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */
/* from sleep.S */
extern int s3c_cpu_save(unsigned long *saveblk);
......@@ -88,6 +90,7 @@ struct pm_uart_save {
u32 ufcon;
u32 umcon;
u32 ubrdiv;
u32 udivslot;
};
/* helper functions to save/restore lists of registers. */
......@@ -124,6 +127,18 @@ extern void s3c_pm_dbg(const char *msg, ...);
#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
#endif
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
/**
* s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
* @set: set bits for the state of the LEDs
* @clear: clear bits for the state of the LEDs.
*/
extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
#else
static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
/* suspend memory checking */
#ifdef CONFIG_S3C2410_PM_CHECK
......
arch/arm/plat-s3c/include/plat/regs-serial.h
View file @ 547c32ae
......@@ -189,6 +189,11 @@
#define S3C2443_DIVSLOT (0x2C)
/* S3C64XX interrupt registers. */
#define S3C64XX_UINTP 0x30
#define S3C64XX_UINTSP 0x34
#define S3C64XX_UINTM 0x38
#ifndef __ASSEMBLY__
/* struct s3c24xx_uart_clksrc
......
arch/arm/plat-s3c/include/plat/sdhci.h
View file @ 547c32ae
......@@ -67,12 +67,52 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
/* Helper function availablity */
extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
/* S3C6400 SDHCI setup */
#ifdef CONFIG_S3C6400_SETUP_SDHCI
extern char *s3c6400_hsmmc_clksrcs[4];
#ifdef CONFIG_S3C_DEV_HSMMC
extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card);
static inline void s3c6400_default_sdhci0(void)
{
s3c_hsmmc0_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
}
#else
static inline void s3c6400_default_sdhci0(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC */
#ifdef CONFIG_S3C_DEV_HSMMC1
static inline void s3c6400_default_sdhci1(void)
{
s3c_hsmmc1_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
}
#else
static inline void s3c6400_default_sdhci1(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC1 */
#else
static inline void s3c6400_default_sdhci0(void) { }
static inline void s3c6400_default_sdhci1(void) { }
#endif /* CONFIG_S3C6400_SETUP_SDHCI */
/* S3C6410 SDHCI setup */
#ifdef CONFIG_S3C6410_SETUP_SDHCI
extern char *s3c6410_hsmmc_clksrcs[4];
extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
......@@ -82,7 +122,7 @@ extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
static inline void s3c6410_default_sdhci0(void)
{
s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
}
#else
......@@ -93,7 +133,7 @@ static inline void s3c6410_default_sdhci0(void) { }
static inline void s3c6410_default_sdhci1(void)
{
s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
}
#else
......
arch/arm/plat-s3c/include/plat/udc-hs.h 0 → 100644
View file @ 547c32ae
/* arch/arm/plat-s3c/include/plat/udc-hs.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C USB2.0 High-speed / OtG platform information
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
enum s3c_hostg_dmamode {
S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */
S3C_HSOTG_DMA_ONLY, /* always use DMA */
S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */
};
/**
* struct s3c_hsotg_plat - platform data for high-speed otg/udc
* @dma: Whether to use DMA or not.
* @is_osc: The clock source is an oscillator, not a crystal
*/
struct s3c_hsotg_plat {
enum s3c_hostg_dmamode dma;
unsigned int is_osc : 1;
};
arch/arm/plat-s3c/include/plat/watchdog-reset.h 0 → 100644
View file @ 547c32ae
/* arch/arm/plat-s3c/include/plat/watchdog-reset.h
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - System define for arch_reset() function
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <plat/regs-watchdog.h>
#include <mach/map.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
static inline void arch_wdt_reset(void)
{
struct clk *wdtclk;
printk("arch_reset: attempting watchdog reset\n");
__raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
wdtclk = clk_get(NULL, "watchdog");
if (!IS_ERR(wdtclk)) {
clk_enable(wdtclk);
} else
printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
/* put initial values into count and data */
__raw_writel(0x80, S3C2410_WTCNT);
__raw_writel(0x80, S3C2410_WTDAT);
/* set the watchdog to go and reset... */
__raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
/* wait for reset to assert... */
mdelay(500);
printk(KERN_ERR "Watchdog reset failed to assert reset\n");
/* delay to allow the serial port to show the message */
mdelay(50);
}
arch/arm/plat-s3c/pm-gpio.c 0 → 100644
View file @ 547c32ae
This diff is collapsed.
arch/arm/plat-s3c/pm.c
View file @ 547c32ae
......@@ -21,11 +21,10 @@
#include <asm/cacheflush.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/regs-serial.h>
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-irq.h>
#include <asm/irq.h>
......@@ -70,6 +69,8 @@ static inline void s3c_pm_debug_init(void)
/* Save the UART configurations if we are configured for debug. */
unsigned char pm_uart_udivslot;
#ifdef CONFIG_S3C2410_PM_DEBUG
struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
......@@ -83,6 +84,12 @@ static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
save->ufcon = __raw_readl(regs + S3C2410_UFCON);
save->umcon = __raw_readl(regs + S3C2410_UMCON);
save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
if (pm_uart_udivslot)
save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
}
static void s3c_pm_save_uarts(void)
......@@ -98,11 +105,16 @@ static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
{
void __iomem *regs = S3C_VA_UARTx(uart);
s3c_pm_arch_update_uart(regs, save);
__raw_writel(save->ulcon, regs + S3C2410_ULCON);
__raw_writel(save->ucon, regs + S3C2410_UCON);
__raw_writel(save->ufcon, regs + S3C2410_UFCON);
__raw_writel(save->umcon, regs + S3C2410_UMCON);
__raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
if (pm_uart_udivslot)
__raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
}
static void s3c_pm_restore_uarts(void)
......@@ -313,6 +325,9 @@ static int s3c_pm_enter(suspend_state_t state)
S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
/* LEDs should now be 1110 */
s3c_pm_debug_smdkled(1 << 1, 0);
s3c_pm_check_restore();
/* ok, let's return from sleep */
......
arch/arm/plat-s3c24xx/Kconfig
View file @ 547c32ae
......@@ -71,6 +71,7 @@ config PM_SIMTEC
config S3C2410_DMA
bool "S3C2410 DMA support"
depends on ARCH_S3C2410
select S3C_DMA
help
S3C2410 DMA support. This is needed for drivers like sound which
use the S3C2410's DMA system to move data to and from the
......
arch/arm/plat-s3c24xx/adc.c
View file @ 547c32ae
......@@ -45,7 +45,8 @@ struct s3c_adc_client {
unsigned char channel;
void (*select_cb)(unsigned selected);
void (*convert_cb)(unsigned val1, unsigned val2);
void (*convert_cb)(unsigned val1, unsigned val2,
unsigned *samples_left);
};
struct adc_device {
......@@ -158,7 +159,8 @@ static void s3c_adc_default_select(unsigned select)
struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
void (*select)(unsigned int selected),
void (*conv)(unsigned d0, unsigned d1),
void (*conv)(unsigned d0, unsigned d1,
unsigned *samples_left),
unsigned int is_ts)
{
struct s3c_adc_client *client;
......@@ -227,9 +229,10 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
data1 = readl(adc->regs + S3C2410_ADCDAT1);
adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
(client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff);
client->nr_samples--;
(client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff, &client->nr_samples);
if (--client->nr_samples > 0) {
if (client->nr_samples > 0) {
/* fire another conversion for this */
client->select_cb(1);
......
arch/arm/plat-s3c24xx/common-smdk.c
View file @ 547c32ae
......@@ -18,6 +18,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/platform_device.h>
......@@ -47,27 +48,27 @@
/* LED devices */
static struct s3c24xx_led_platdata smdk_pdata_led4 = {
.gpio = S3C2410_GPF4,
.gpio = S3C2410_GPF(4),
.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.name = "led4",
.def_trigger = "timer",
};
static struct s3c24xx_led_platdata smdk_pdata_led5 = {
.gpio = S3C2410_GPF5,
.gpio = S3C2410_GPF(5),
.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.name = "led5",
.def_trigger = "nand-disk",
};
static struct s3c24xx_led_platdata smdk_pdata_led6 = {
.gpio = S3C2410_GPF6,
.gpio = S3C2410_GPF(6),
.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.name = "led6",
};
static struct s3c24xx_led_platdata smdk_pdata_led7 = {
.gpio = S3C2410_GPF7,
.gpio = S3C2410_GPF(7),
.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.name = "led7",
};
......@@ -184,15 +185,15 @@ void __init smdk_machine_init(void)
{
/* Configure the LEDs (even if we have no LED support)*/
s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP);
s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP);
s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP);
s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP);
s3c2410_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_setpin(S3C2410_GPF4, 1);
s3c2410_gpio_setpin(S3C2410_GPF5, 1);
s3c2410_gpio_setpin(S3C2410_GPF6, 1);
s3c2410_gpio_setpin(S3C2410_GPF7, 1);
s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
s3c2410_gpio_setpin(S3C2410_GPF(6), 1);
s3c2410_gpio_setpin(S3C2410_GPF(7), 1);
if (machine_is_smdk2443())
smdk_nand_info.twrph0 = 50;
......
arch/arm/plat-s3c24xx/devs.c
View file @ 547c32ae
......@@ -136,36 +136,6 @@ struct platform_device *s3c24xx_uart_src[4] = {
struct platform_device *s3c24xx_uart_devs[4] = {
};
/* USB Host Controller */
static struct resource s3c_usb_resource[] = {
[0] = {
.start = S3C24XX_PA_USBHOST,
.end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_USBH,
.end = IRQ_USBH,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_usb_dmamask = 0xffffffffUL;
struct platform_device s3c_device_usb = {
.name = "s3c2410-ohci",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_usb_resource),
.resource = s3c_usb_resource,
.dev = {
.dma_mask = &s3c_device_usb_dmamask,
.coherent_dma_mask = 0xffffffffUL
}
};
EXPORT_SYMBOL(s3c_device_usb);
/* LCD Controller */
static struct resource s3c_lcd_resource[] = {
......
arch/arm/plat-s3c24xx/dma.c
View file @ 547c32ae
This diff is collapsed.
arch/arm/plat-s3c24xx/gpio.c
View file @ 547c32ae
......@@ -183,35 +183,19 @@ EXPORT_SYMBOL(s3c2410_modify_misccr);
int s3c2410_gpio_getirq(unsigned int pin)
{
if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15)
return -1; /* not valid interrupts */
if (pin < S3C2410_GPF(0) || pin > S3C2410_GPG(15))
return -EINVAL; /* not valid interrupts */
if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
return -1; /* not valid pin */
if (pin < S3C2410_GPG(0) && pin > S3C2410_GPF(7))
return -EINVAL; /* not valid pin */
if (pin < S3C2410_GPF4)
return (pin - S3C2410_GPF0) + IRQ_EINT0;
if (pin < S3C2410_GPF(4))
return (pin - S3C2410_GPF(0)) + IRQ_EINT0;
if (pin < S3C2410_GPG0)
return (pin - S3C2410_GPF4) + IRQ_EINT4;
if (pin < S3C2410_GPG(0))
return (pin - S3C2410_GPF(4)) + IRQ_EINT4;
return (pin - S3C2410_GPG0) + IRQ_EINT8;
return (pin - S3C2410_GPG(0)) + IRQ_EINT8;
}
EXPORT_SYMBOL(s3c2410_gpio_getirq);
int s3c2410_gpio_irq2pin(unsigned int irq)
{
if (irq >= IRQ_EINT0 && irq <= IRQ_EINT3)
return S3C2410_GPF0 + (irq - IRQ_EINT0);
if (irq >= IRQ_EINT4 && irq <= IRQ_EINT7)
return S3C2410_GPF4 + (irq - IRQ_EINT4);
if (irq >= IRQ_EINT8 && irq <= IRQ_EINT23)
return S3C2410_GPG0 + (irq - IRQ_EINT8);
return -EINVAL;
}
EXPORT_SYMBOL(s3c2410_gpio_irq2pin);
arch/arm/plat-s3c24xx/gpiolib.c
View file @ 547c32ae
This diff is collapsed.
arch/arm/plat-s3c24xx/include/plat/dma.h → arch/arm/plat-s3c24xx/include/plat/dma-plat.h
View file @ 547c32ae
/* linux/include/asm-arm/plat-s3c24xx/dma.h
/* linux/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
*
* Copyright (C) 2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
......@@ -10,8 +10,10 @@
* published by the Free Software Foundation.
*/
#include <plat/dma-core.h>
extern struct sysdev_class dma_sysclass;
extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
#define DMA_CH_VALID (1<<31)
#define DMA_CH_NEVER (1<<30)
......@@ -31,8 +33,8 @@ struct s3c24xx_dma_map {
const char *name;
struct s3c24xx_dma_addr hw_addr;
unsigned long channels[S3C2410_DMA_CHANNELS];
unsigned long channels_rx[S3C2410_DMA_CHANNELS];
unsigned long channels[S3C_DMA_CHANNELS];
unsigned long channels_rx[S3C_DMA_CHANNELS];
};
struct s3c24xx_dma_selection {
......@@ -58,7 +60,7 @@ extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
*/
struct s3c24xx_dma_order_ch {
unsigned int list[S3C2410_DMA_CHANNELS]; /* list of channels */
unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */
unsigned int flags; /* flags */
};
......
arch/arm/plat-s3c24xx/include/plat/map.h
View file @ 547c32ae
......@@ -58,7 +58,6 @@
#define S3C24XX_SZ_SPI SZ_1M
#define S3C24XX_SZ_SDI SZ_1M
#define S3C24XX_SZ_NAND SZ_1M
#define S3C24XX_SZ_USBHOST SZ_1M
/* GPIO ports */
......
arch/arm/plat-s3c24xx/include/plat/pm-core.h
View file @ 547c32ae
......@@ -57,3 +57,8 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
s3c_irqwake_eintmask);
}
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save)
{
}
arch/arm/plat-s3c24xx/include/plat/regs-dma.h 0 → 100644
View file @ 547c32ae
This diff is collapsed.
arch/arm/plat-s3c24xx/pm.c
View file @ 547c32ae
This diff is collapsed.
arch/arm/plat-s3c24xx/setup-i2c.c
View file @ 547c32ae
......@@ -11,6 +11,7 @@
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
struct platform_device;
......@@ -20,6 +21,6 @@ struct platform_device;
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
}
arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
View file @ 547c32ae
......@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
int enable)
{
if (enable) {
s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0);
s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0);
s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0);
s3c2410_gpio_pullup(S3C2410_GPE11, 0);
s3c2410_gpio_pullup(S3C2410_GPE13, 0);
s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
s3c2410_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
} else {
s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT);
s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT);
s3c2410_gpio_pullup(S3C2410_GPE11, 1);
s3c2410_gpio_pullup(S3C2410_GPE12, 1);
s3c2410_gpio_pullup(S3C2410_GPE13, 1);
s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
s3c2410_gpio_pullup(S3C2410_GPE(11), 1);
s3c2410_gpio_pullup(S3C2410_GPE(12), 1);
s3c2410_gpio_pullup(S3C2410_GPE(13), 1);
}
}
arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
View file @ 547c32ae
......@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
int enable)
{
if (enable) {
s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1);
s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1);
s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1);
s3c2410_gpio_pullup(S3C2410_GPG5, 0);
s3c2410_gpio_pullup(S3C2410_GPG6, 0);
s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
s3c2410_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
} else {
s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT);
s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT);
s3c2410_gpio_pullup(S3C2410_GPG5, 1);
s3c2410_gpio_pullup(S3C2410_GPG6, 1);
s3c2410_gpio_pullup(S3C2410_GPG7, 1);
s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
s3c2410_gpio_pullup(S3C2410_GPG(5), 1);
s3c2410_gpio_pullup(S3C2410_GPG(6), 1);
s3c2410_gpio_pullup(S3C2410_GPG(7), 1);
}
}
arch/arm/plat-s3c64xx/Kconfig
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arch/arm/plat-s3c64xx/Makefile
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arch/arm/plat-s3c64xx/clock.c
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arch/arm/plat-s3c64xx/cpu.c
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arch/arm/plat-s3c64xx/dma.c 0 → 100644
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arch/arm/plat-s3c64xx/gpiolib.c
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arch/arm/plat-s3c64xx/include/plat/dma-plat.h 0 → 100644
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arch/arm/plat-s3c64xx/include/plat/irqs.h
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arch/arm/plat-s3c64xx/include/plat/pm-core.h 0 → 100644
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arch/arm/plat-s3c64xx/irq-eint.c
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arch/arm/plat-s3c64xx/irq-pm.c 0 → 100644
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arch/arm/plat-s3c64xx/irq.c
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arch/arm/plat-s3c64xx/pm.c 0 → 100644
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arch/arm/plat-s3c64xx/s3c6400-clock.c
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arch/arm/plat-s3c64xx/setup-sdhci-gpio.c 0 → 100644
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arch/arm/plat-s3c64xx/sleep.S 0 → 100644
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drivers/leds/leds-h1940.c
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drivers/leds/leds-s3c24xx.c
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drivers/mmc/host/s3cmci.c
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drivers/spi/spi_s3c24xx_gpio.c
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sound/soc/s3c24xx/s3c2412-i2s.c
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sound/soc/s3c24xx/s3c2443-ac97.c
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sound/soc/s3c24xx/s3c24xx-i2s.c
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sound/soc/s3c24xx/s3c24xx-pcm.c
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