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nexedi
linux
Commits
54a751f6
Commit
54a751f6
authored
Dec 17, 2019
by
Tony Lindgren
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Merge branch 'omap-for-v5.6/ti-sysc-dt' into omap-for-v5.6/ti-sysc-drop-pdata
parents
d864dbdf
a6c8056d
Changes
6
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6 changed files
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233 additions
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83 deletions
+233
-83
arch/arm/boot/dts/dra7.dtsi
arch/arm/boot/dts/dra7.dtsi
+108
-32
arch/arm/boot/dts/dra74x.dtsi
arch/arm/boot/dts/dra74x.dtsi
+55
-16
arch/arm/boot/dts/omap4-l4.dtsi
arch/arm/boot/dts/omap4-l4.dtsi
+8
-3
arch/arm/boot/dts/omap4.dtsi
arch/arm/boot/dts/omap4.dtsi
+28
-15
arch/arm/boot/dts/omap5-l4.dtsi
arch/arm/boot/dts/omap5-l4.dtsi
+8
-3
arch/arm/boot/dts/omap5.dtsi
arch/arm/boot/dts/omap5.dtsi
+26
-14
No files found.
arch/arm/boot/dts/dra7.dtsi
View file @
54a751f6
...
@@ -377,44 +377,120 @@ dmm@4e000000 {
...
@@ -377,44 +377,120 @@ dmm@4e000000 {
ti,hwmods = "dmm";
ti,hwmods = "dmm";
};
};
mmu0_dsp1: mmu@40d01000 {
target-module@40d01000 {
compatible = "ti,dra7-dsp-iommu";
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x40d01000 0x100>;
reg = <0x40d01000 0x4>,
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
<0x40d01010 0x4>,
ti,hwmods = "mmu0_dsp1";
<0x40d01014 0x4>;
#iommu-cells = <0>;
reg-names = "rev", "sysc", "syss";
ti,syscon-mmuconfig = <&dsp1_system 0x0>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
status = "disabled";
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp1 1>;
reset-names = "rstctrl";
ranges = <0x0 0x40d01000 0x1000>;
#size-cells = <1>;
#address-cells = <1>;
mmu0_dsp1: mmu@0 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x0>;
};
};
};
mmu1_dsp1: mmu@40d02000 {
target-module@40d02000 {
compatible = "ti,dra7-dsp-iommu";
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x40d02000 0x100>;
reg = <0x40d02000 0x4>,
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
<0x40d02010 0x4>,
ti,hwmods = "mmu1_dsp1";
<0x40d02014 0x4>;
#iommu-cells = <0>;
reg-names = "rev", "sysc", "syss";
ti,syscon-mmuconfig = <&dsp1_system 0x1>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
status = "disabled";
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp1 1>;
reset-names = "rstctrl";
ranges = <0x0 0x40d02000 0x1000>;
#size-cells = <1>;
#address-cells = <1>;
mmu1_dsp1: mmu@0 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x1>;
};
};
};
mmu_ipu1: mmu@58882000 {
target-module@58882000 {
compatible = "ti,dra7-iommu";
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x58882000 0x100>;
reg = <0x58882000 0x4>,
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
<0x58882010 0x4>,
ti,hwmods = "mmu_ipu1";
<0x58882014 0x4>;
#iommu-cells = <0>;
reg-names = "rev", "sysc", "syss";
ti,iommu-bus-err-back;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
status = "disabled";
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_ipu 2>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x58882000 0x100>;
mmu_ipu1: mmu@0 {
compatible = "ti,dra7-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,iommu-bus-err-back;
};
};
};
mmu_ipu2: mmu@55082000 {
target-module@55082000 {
compatible = "ti,dra7-iommu";
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55082000 0x100>;
reg = <0x55082000 0x4>,
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
<0x55082010 0x4>,
ti,hwmods = "mmu_ipu2";
<0x55082014 0x4>;
#iommu-cells = <0>;
reg-names = "rev", "sysc", "syss";
ti,iommu-bus-err-back;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
status = "disabled";
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_core 2>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x55082000 0x100>;
mmu_ipu2: mmu@0 {
compatible = "ti,dra7-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,iommu-bus-err-back;
};
};
};
abb_mpu: regulator-abb-mpu {
abb_mpu: regulator-abb-mpu {
...
...
arch/arm/boot/dts/dra74x.dtsi
View file @
54a751f6
...
@@ -66,24 +66,63 @@ usb4: usb@48950000 {
...
@@ -66,24 +66,63 @@ usb4: usb@48950000 {
};
};
};
};
mmu0_dsp2: mmu@41501000 {
target-module@41501000 {
compatible = "ti,dra7-dsp-iommu";
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x41501000 0x100>;
reg = <0x41501000 0x4>,
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
<0x41501010 0x4>,
ti,hwmods = "mmu0_dsp2";
<0x41501014 0x4>;
#iommu-cells = <0>;
reg-names = "rev", "sysc", "syss";
ti,syscon-mmuconfig = <&dsp2_system 0x0>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
status = "disabled";
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp2 1>;
reset-names = "rstctrl";
ranges = <0x0 0x41501000 0x1000>;
#size-cells = <1>;
#address-cells = <1>;
mmu0_dsp2: mmu@0 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x0>;
};
};
};
mmu1_dsp2: mmu@41502000 {
target-module@41502000 {
compatible = "ti,dra7-dsp-iommu";
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x41502000 0x100>;
reg = <0x41502000 0x4>,
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
<0x41502010 0x4>,
ti,hwmods = "mmu1_dsp2";
<0x41502014 0x4>;
#iommu-cells = <0>;
reg-names = "rev", "sysc", "syss";
ti,syscon-mmuconfig = <&dsp2_system 0x1>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
status = "disabled";
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp2 1>;
reset-names = "rstctrl";
ranges = <0x0 0x41502000 0x1000>;
#size-cells = <1>;
#address-cells = <1>;
mmu1_dsp2: mmu@0 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x1>;
};
};
};
};
};
};
};
...
...
arch/arm/boot/dts/omap4-l4.dtsi
View file @
54a751f6
...
@@ -320,7 +320,6 @@ usbhsehci: ehci@c00 {
...
@@ -320,7 +320,6 @@ usbhsehci: ehci@c00 {
target-module@66000 { /* 0x4a066000, ap 25 26.0 */
target-module@66000 { /* 0x4a066000, ap 25 26.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mmu_dsp";
reg = <0x66000 0x4>,
reg = <0x66000 0x4>,
<0x66010 0x4>,
<0x66010 0x4>,
<0x66014 0x4>;
<0x66014 0x4>;
...
@@ -334,12 +333,18 @@ SYSC_OMAP2_SOFTRESET |
...
@@ -334,12 +333,18 @@ SYSC_OMAP2_SOFTRESET |
/* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
/* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
clock-names = "fck";
clock-names = "fck";
resets = <&prm_tesla 1>;
reset-names = "rstctrl";
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x66000 0x1000>;
ranges = <0x0 0x66000 0x1000>;
/* mmu_dsp cannot be moved before reset driver */
mmu_dsp: mmu@0 {
status = "disabled";
compatible = "ti,omap4-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
};
};
};
};
};
...
...
arch/arm/boot/dts/omap4.dtsi
View file @
54a751f6
...
@@ -173,14 +173,6 @@ gpmc: gpmc@50000000 {
...
@@ -173,14 +173,6 @@ gpmc: gpmc@50000000 {
#gpio-cells = <2>;
#gpio-cells = <2>;
};
};
mmu_dsp: mmu@4a066000 {
compatible = "ti,omap4-iommu";
reg = <0x4a066000 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_dsp";
#iommu-cells = <0>;
};
target-module@52000000 {
target-module@52000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "iss";
ti,hwmods = "iss";
...
@@ -206,14 +198,35 @@ target-module@52000000 {
...
@@ -206,14 +198,35 @@ target-module@52000000 {
/* No child device binding, driver in staging */
/* No child device binding, driver in staging */
};
};
mmu_ipu: mmu@55082000 {
target-module@55082000 {
compatible = "ti,omap4-iommu";
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55082000 0x100>;
reg = <0x55082000 0x4>,
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
<0x55082010 0x4>,
ti,hwmods = "mmu_ipu";
<0x55082014 0x4>;
#iommu-cells = <0>;
reg-names = "rev", "sysc", "syss";
ti,iommu-bus-err-back;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_core 2>;
reset-names = "rstctrl";
ranges = <0x0 0x55082000 0x100>;
#size-cells = <1>;
#address-cells = <1>;
mmu_ipu: mmu@0 {
compatible = "ti,omap4-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,iommu-bus-err-back;
};
};
};
target-module@4012c000 {
target-module@4012c000 {
compatible = "ti,sysc-omap4", "ti,sysc";
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x4012c000 0x4>,
reg = <0x4012c000 0x4>,
...
...
arch/arm/boot/dts/omap5-l4.dtsi
View file @
54a751f6
...
@@ -349,7 +349,6 @@ usbhsehci: ehci@c00 {
...
@@ -349,7 +349,6 @@ usbhsehci: ehci@c00 {
target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mmu_dsp";
reg = <0x66000 0x4>,
reg = <0x66000 0x4>,
<0x66010 0x4>,
<0x66010 0x4>,
<0x66014 0x4>;
<0x66014 0x4>;
...
@@ -364,12 +363,18 @@ SYSC_OMAP2_SOFTRESET |
...
@@ -364,12 +363,18 @@ SYSC_OMAP2_SOFTRESET |
/* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
/* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
clock-names = "fck";
clock-names = "fck";
resets = <&prm_dsp 1>;
reset-names = "rstctrl";
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x66000 0x1000>;
ranges = <0x0 0x66000 0x1000>;
/* mmu_dsp cannot be moved before reset driver */
mmu_dsp: mmu@0 {
status = "disabled";
compatible = "ti,omap4-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
};
};
};
target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
...
...
arch/arm/boot/dts/omap5.dtsi
View file @
54a751f6
...
@@ -186,21 +186,33 @@ gpmc: gpmc@50000000 {
...
@@ -186,21 +186,33 @@ gpmc: gpmc@50000000 {
#gpio-cells = <2>;
#gpio-cells = <2>;
};
};
mmu_dsp: mmu@4a066000 {
target-module@55082000 {
compatible = "ti,omap4-iommu";
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4a066000 0x100>;
reg = <0x55082000 0x4>,
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
<0x55082010 0x4>,
ti,hwmods = "mmu_dsp";
<0x55082014 0x4>;
#iommu-cells = <0>;
reg-names = "rev", "sysc", "syss";
};
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_core 2>;
reset-names = "rstctrl";
ranges = <0x0 0x55082000 0x100>;
#size-cells = <1>;
#address-cells = <1>;
mmu_ipu: mmu@5508200
0 {
mmu_ipu: mmu@
0 {
compatible = "ti,omap4-iommu";
compatible = "ti,omap4-iommu";
reg = <0x5508200
0 0x100>;
reg = <0x
0 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu"
;
#iommu-cells = <0>
;
#iommu-cells = <0>
;
ti,iommu-bus-err-back
;
ti,iommu-bus-err-back
;
}
;
};
};
dmm@4e000000 {
dmm@4e000000 {
...
...
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