Merge branch 'dts-cpus-updates' of git://linux-arm.org/linux-2.6-lp into next/dt

From Lorenzo Pieralisi, this is a series of patches that cleans up the CPU
nodes in most of the SoC dtsi files to conform to the standard bindings.

* 'dts-cpus-updates' of git://linux-arm.org/linux-2.6-lp:
  ARM: dts: sunxi: cpus/cpu nodes dts updates
  ARM: dts: spear: cpus/cpu nodes dts updates
  ARM: dts: sh7372: cpus/cpu nodes dts updates
  ARM: dts: r8a7740: cpus/cpu nodes dts updates
  ARM: dts: pxa2xx: cpus/cpu nodes dts updates
  ARM: dts: prima2: cpus/cpu node dts updates
  ARM: dts: picoxcell: cpus/cpu nodes dts updates
  ARM: dts: omap: cpus/cpu nodes dts updates
  ARM: dts: lpc32xx: cpus/cpu nodes dts updates
  ARM: dts: imx: cpus/cpu nodes dts updates
  ARM: dts: exynos5440: cpus/cpu nodes dts updates
  ARM: dts: at91: cpus/cpu node dts updates
  ARM: dts: armada-370-xp: cpus/cpu node dts updates
  ARM: dts: am33xx: cpus/cpu nodes dts updates
Signed-off-by: Olof Johansson <olof@lixom.net>

arch/arm/boot/dts/am33xx.dtsi

@@ -26,8 +26,12 @@ aliases {
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		cpu@0 {
 			compatible = "arm,cortex-a8";
+			device_type = "cpu";
+			reg = <0>;
 
 			/*
 			 * To consider voltage drop between PMIC and SoC,

arch/arm/boot/dts/armada-370-xp.dtsi

@@ -23,8 +23,12 @@ / {
 	compatible = "marvell,armada-370-xp";
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		cpu@0 {
 			compatible = "marvell,sheeva-v7";
+			device_type = "cpu";
+			reg = <0>;
 		};
 	};
 

arch/arm/boot/dts/at91rm9200.dtsi

@@ -38,8 +38,12 @@ aliases {
 		ssc2 = &ssc2;
 	};
 	cpus {
-		cpu@0 {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
 			compatible = "arm,arm920t";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/at91sam9260.dtsi

@@ -35,8 +35,12 @@ aliases {
 		ssc0 = &ssc0;
 	};
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/at91sam9263.dtsi

@@ -32,8 +32,12 @@ aliases {
 		ssc1 = &ssc1;
 	};
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/at91sam9g45.dtsi

@@ -38,8 +38,12 @@ aliases {
 		ssc1 = &ssc1;
 	};
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/at91sam9n12.dtsi

@@ -34,8 +34,12 @@ aliases {
 		ssc0 = &ssc0;
 	};
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/at91sam9x5.dtsi

@@ -36,8 +36,12 @@ aliases {
 		ssc0 = &ssc0;
 	};
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/exynos5440.dtsi

@@ -38,18 +38,22 @@ cpus {
 		#size-cells = <0>;
 
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0>;
 		};
 		cpu@1 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <1>;
 		};
 		cpu@2 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <2>;
 		};
 		cpu@3 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <3>;
 		};

arch/arm/boot/dts/imx23.dtsi

@@ -23,8 +23,12 @@ aliases {
 	};
 
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/imx28.dtsi

@@ -32,8 +32,12 @@ aliases {
 	};
 
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/imx6dl.dtsi

@@ -18,12 +18,14 @@ cpus {
 
 		cpu@0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <0>;
 			next-level-cache = <&L2>;
 		};
 
 		cpu@1 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
 		};

arch/arm/boot/dts/imx6q.dtsi

@@ -18,6 +18,7 @@ cpus {
 
 		cpu@0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <0>;
 			next-level-cache = <&L2>;
 			operating-points = <
@@ -39,18 +40,21 @@ cpu@0 {
 
 		cpu@1 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
 		};
 
 		cpu@2 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <2>;
 			next-level-cache = <&L2>;
 		};
 
 		cpu@3 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <3>;
 			next-level-cache = <&L2>;
 		};

arch/arm/boot/dts/lpc32xx.dtsi

@@ -18,8 +18,12 @@ / {
 	interrupt-parent = <&mic>;
 
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/omap2.dtsi

@@ -21,8 +21,12 @@ aliases {
 	};
 
 	cpus {
-		cpu@0 {
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
 			compatible = "arm,arm1136jf-s";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/omap3.dtsi

@@ -21,8 +21,13 @@ aliases {
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "arm,cortex-a8";
+			device_type = "cpu";
+			reg = <0x0>;
 		};
 	};
 

arch/arm/boot/dts/omap4.dtsi

@@ -28,13 +28,20 @@ aliases {
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			next-level-cache = <&L2>;
+			reg = <0x0>;
 		};
 		cpu@1 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			next-level-cache = <&L2>;
+			reg = <0x1>;
 		};
 	};
 

arch/arm/boot/dts/omap5.dtsi

@@ -34,11 +34,18 @@ aliases {
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a15";
+			reg = <0x0>;
 		};
 		cpu@1 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a15";
+			reg = <0x1>;
 		};
 	};
 

arch/arm/boot/dts/picoxcell-pc3x2.dtsi

@@ -18,13 +18,13 @@ / {
 	#size-cells = <1>;
 
 	cpus {
-		#address-cells = <1>;
+		#address-cells = <0>;
 		#size-cells = <0>;
 
-		cpu@0 {
-			compatible = "arm,1176jz-s";
+		cpu {
+			compatible = "arm,arm1176jz-s";
+			device_type = "cpu";
 			clock-frequency = <400000000>;
-			reg = <0>;
 			d-cache-line-size = <32>;
 			d-cache-size = <32768>;
 			i-cache-line-size = <32>;

arch/arm/boot/dts/picoxcell-pc3x3.dtsi

@@ -18,13 +18,13 @@ / {
 	#size-cells = <1>;
 
 	cpus {
-		#address-cells = <1>;
+		#address-cells = <0>;
 		#size-cells = <0>;
 
-		cpu@0 {
-			compatible = "arm,1176jz-s";
+		cpu {
+			compatible = "arm,arm1176jz-s";
+			device_type = "cpu";
 			cpu-clock = <&arm_clk>, "cpu";
-			reg = <0>;
 			d-cache-line-size = <32>;
 			d-cache-size = <32768>;
 			i-cache-line-size = <32>;

arch/arm/boot/dts/prima2.dtsi

@@ -18,6 +18,8 @@ cpus {
 		#size-cells = <0>;
 
 		cpu@0 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <0x0>;
 			d-cache-line-size = <32>;
 			i-cache-line-size = <32>;

arch/arm/boot/dts/pxa2xx.dtsi

@@ -23,8 +23,11 @@ aliases {
 	};
 
 	cpus {
-		cpu@0 {
-			compatible = "arm,xscale";
+		#address-cells = <0>;
+		#size-cells = <0>;
+		cpu {
+			compatible = "marvell,xscale";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/r8a7740.dtsi

@@ -14,8 +14,12 @@ / {
 	compatible = "renesas,r8a7740";
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
 		cpu@0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <0x0>;
 		};
 	};
 };

arch/arm/boot/dts/sama5d3.dtsi

@@ -39,7 +39,9 @@ aliases {
 	};
 	cpus {
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a5";
+			reg = <0x0>;
 		};
 	};
 

arch/arm/boot/dts/sh7372.dtsi

@@ -14,8 +14,13 @@ / {
 	compatible = "renesas,sh7372";
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "arm,cortex-a8";
+			device_type = "cpu";
+			reg = <0x0>;
 		};
 	};
 };

arch/arm/boot/dts/spear13xx.dtsi

@@ -22,12 +22,14 @@ cpus {
 
 		cpu@0 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <0>;
 			next-level-cache = <&L2>;
 		};
 
 		cpu@1 {
 			compatible = "arm,cortex-a9";
+			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
 		};

arch/arm/boot/dts/spear3xx.dtsi

@@ -17,8 +17,12 @@ / {
 	interrupt-parent = <&vic>;
 
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/spear600.dtsi

@@ -15,8 +15,12 @@ / {
 	compatible = "st,spear600";
 
 	cpus {
-		cpu@0 {
-			compatible = "arm,arm926ejs";
+		#address-cells = <0>;
+		#size-cells = <0>;
+
+		cpu {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/sun4i-a10.dtsi

@@ -17,7 +17,9 @@ / {
 
 	cpus {
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a8";
+			reg = <0x0>;
 		};
 	};
 

arch/arm/boot/dts/sun5i-a13.dtsi

@@ -18,7 +18,9 @@ / {
 
 	cpus {
 		cpu@0 {
+			device_type = "cpu";
 			compatible = "arm,cortex-a8";
+			reg = <0x0>;
 		};
 	};