Commit 54fb1742 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard

drm/sun4i: Add compatible strings for the A80 display pipeline

This patch adds compatible strings for the remaining documented
components of the Allwinner A80 display pipeline.
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180315114136.24747-5-wens@csie.org
parent 6664e9dc
...@@ -191,7 +191,7 @@ DRC ...@@ -191,7 +191,7 @@ DRC
--- ---
The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
(A31, A23, A33), allows to dynamically adjust pixel (A31, A23, A33, A80), allows to dynamically adjust pixel
brightness/contrast based on histogram measurements for LCD content brightness/contrast based on histogram measurements for LCD content
adaptive backlight control. adaptive backlight control.
...@@ -201,6 +201,7 @@ Required properties: ...@@ -201,6 +201,7 @@ Required properties:
* allwinner,sun6i-a31-drc * allwinner,sun6i-a31-drc
* allwinner,sun6i-a31s-drc * allwinner,sun6i-a31s-drc
* allwinner,sun8i-a33-drc * allwinner,sun8i-a33-drc
* allwinner,sun9i-a80-drc
- reg: base address and size of the memory-mapped region. - reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP - interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the DRC - clocks: phandles to the clocks feeding the DRC
...@@ -227,6 +228,7 @@ Required properties: ...@@ -227,6 +228,7 @@ Required properties:
* allwinner,sun6i-a31-display-backend * allwinner,sun6i-a31-display-backend
* allwinner,sun7i-a20-display-backend * allwinner,sun7i-a20-display-backend
* allwinner,sun8i-a33-display-backend * allwinner,sun8i-a33-display-backend
* allwinner,sun9i-a80-display-backend
- reg: base address and size of the memory-mapped region. - reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP - interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the frontend and backend - clocks: phandles to the clocks feeding the frontend and backend
...@@ -283,6 +285,7 @@ Required properties: ...@@ -283,6 +285,7 @@ Required properties:
* allwinner,sun6i-a31-display-frontend * allwinner,sun6i-a31-display-frontend
* allwinner,sun7i-a20-display-frontend * allwinner,sun7i-a20-display-frontend
* allwinner,sun8i-a33-display-frontend * allwinner,sun8i-a33-display-frontend
* allwinner,sun9i-a80-display-frontend
- reg: base address and size of the memory-mapped region. - reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP - interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the frontend and backend - clocks: phandles to the clocks feeding the frontend and backend
...@@ -339,6 +342,7 @@ Required properties: ...@@ -339,6 +342,7 @@ Required properties:
* allwinner,sun8i-a83t-display-engine * allwinner,sun8i-a83t-display-engine
* allwinner,sun8i-h3-display-engine * allwinner,sun8i-h3-display-engine
* allwinner,sun8i-v3s-display-engine * allwinner,sun8i-v3s-display-engine
* allwinner,sun9i-a80-display-engine
- allwinner,pipelines: list of phandle to the display engine - allwinner,pipelines: list of phandle to the display engine
frontends (DE 1.0) or mixers (DE 2.0) available. frontends (DE 1.0) or mixers (DE 2.0) available.
......
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