Commit 568a0a96 authored by Gilles DOFFE's avatar Gilles DOFFE Committed by Shawn Guo

ARM: dts: imx6qdl-rex: add gpio expander pca9535

The pca9535 gpio expander is present on the Rex baseboard, but missing
from the dtsi.
The pca9535 is on i2c2 bus which is common to the three SOM
variants (Basic/Pro/Ultra), thus it is activated by default.

Add also the new gpio controller and the associated interrupt line
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16.
Signed-off-by: default avatarGilles DOFFE <gilles.doffe@savoirfairelinux.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent b780317d
...@@ -132,6 +132,19 @@ &i2c2 { ...@@ -132,6 +132,19 @@ &i2c2 {
pinctrl-0 = <&pinctrl_i2c2>; pinctrl-0 = <&pinctrl_i2c2>;
status = "okay"; status = "okay";
pca9535: gpio-expander@27 {
compatible = "nxp,pca9535";
reg = <0x27>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9535>;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
};
eeprom@57 { eeprom@57 {
compatible = "atmel,24c02"; compatible = "atmel,24c02";
reg = <0x57>; reg = <0x57>;
...@@ -237,6 +250,12 @@ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 ...@@ -237,6 +250,12 @@ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
>; >;
}; };
pinctrl_pca9535: pca9535grp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059
>;
};
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
......
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