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nexedi
linux
Commits
5693c0f2
Commit
5693c0f2
authored
May 12, 2014
by
Ben Skeggs
Browse files
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Email Patches
Plain Diff
drm/nouveau/gpio: split "toggled" interrupt into "went high" / "went low"
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
7356859a
Changes
7
Hide whitespace changes
Inline
Side-by-side
Showing
7 changed files
with
156 additions
and
114 deletions
+156
-114
drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
+39
-3
drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c
drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c
+15
-27
drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c
drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c
+18
-42
drivers/gpu/drm/nouveau/core/subdev/gpio/nv92.c
drivers/gpu/drm/nouveau/core/subdev/gpio/nv92.c
+35
-1
drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c
drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c
+2
-4
drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c
drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c
+27
-34
drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h
drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h
+20
-3
No files found.
drivers/gpu/drm/nouveau/core/subdev/gpio/base.c
View file @
5693c0f2
...
@@ -103,6 +103,37 @@ nouveau_gpio_get(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line)
...
@@ -103,6 +103,37 @@ nouveau_gpio_get(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line)
return
ret
;
return
ret
;
}
}
static
void
nouveau_gpio_intr_disable
(
struct
nouveau_event
*
event
,
int
type
,
int
index
)
{
struct
nouveau_gpio
*
gpio
=
nouveau_gpio
(
event
->
priv
);
const
struct
nouveau_gpio_impl
*
impl
=
(
void
*
)
nv_object
(
gpio
)
->
oclass
;
impl
->
intr_mask
(
gpio
,
NVKM_GPIO_TOGGLED
,
1
<<
index
,
0
);
}
static
void
nouveau_gpio_intr_enable
(
struct
nouveau_event
*
event
,
int
type
,
int
index
)
{
struct
nouveau_gpio
*
gpio
=
nouveau_gpio
(
event
->
priv
);
const
struct
nouveau_gpio_impl
*
impl
=
(
void
*
)
nv_object
(
gpio
)
->
oclass
;
impl
->
intr_mask
(
gpio
,
NVKM_GPIO_TOGGLED
,
1
<<
index
,
1
<<
index
);
}
static
void
nouveau_gpio_intr
(
struct
nouveau_subdev
*
subdev
)
{
struct
nouveau_gpio
*
gpio
=
nouveau_gpio
(
subdev
);
const
struct
nouveau_gpio_impl
*
impl
=
(
void
*
)
nv_object
(
gpio
)
->
oclass
;
u32
hi
,
lo
,
i
;
impl
->
intr_stat
(
gpio
,
&
hi
,
&
lo
);
for
(
i
=
0
;
(
hi
|
lo
)
&&
i
<
impl
->
lines
;
i
++
)
{
if
((
hi
|
lo
)
&
(
1
<<
i
))
nouveau_event_trigger
(
gpio
->
events
,
1
,
i
);
}
}
void
void
_nouveau_gpio_dtor
(
struct
nouveau_object
*
object
)
_nouveau_gpio_dtor
(
struct
nouveau_object
*
object
)
{
{
...
@@ -127,13 +158,18 @@ nouveau_gpio_create_(struct nouveau_object *parent,
...
@@ -127,13 +158,18 @@ nouveau_gpio_create_(struct nouveau_object *parent,
if
(
ret
)
if
(
ret
)
return
ret
;
return
ret
;
gpio
->
find
=
nouveau_gpio_find
;
gpio
->
set
=
nouveau_gpio_set
;
gpio
->
get
=
nouveau_gpio_get
;
ret
=
nouveau_event_create
(
1
,
impl
->
lines
,
&
gpio
->
events
);
ret
=
nouveau_event_create
(
1
,
impl
->
lines
,
&
gpio
->
events
);
if
(
ret
)
if
(
ret
)
return
ret
;
return
ret
;
gpio
->
find
=
nouveau_gpio_find
;
gpio
->
events
->
priv
=
gpio
;
gpio
->
set
=
nouveau_gpio_set
;
gpio
->
events
->
enable
=
nouveau_gpio_intr_enable
;
gpio
->
get
=
nouveau_gpio_get
;
gpio
->
events
->
disable
=
nouveau_gpio_intr_disable
;
nv_subdev
(
gpio
)
->
intr
=
nouveau_gpio_intr
;
return
0
;
return
0
;
}
}
...
...
drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c
View file @
5693c0f2
...
@@ -83,34 +83,24 @@ nv10_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
...
@@ -83,34 +83,24 @@ nv10_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
}
}
static
void
static
void
nv10_gpio_intr
(
struct
nouveau_subdev
*
subdev
)
nv10_gpio_intr
_stat
(
struct
nouveau_gpio
*
gpio
,
u32
*
hi
,
u32
*
lo
)
{
{
struct
nv10_gpio_priv
*
priv
=
(
void
*
)
subdev
;
u32
intr
=
nv_rd32
(
gpio
,
0x001104
);
u32
intr
=
nv_rd32
(
priv
,
0x001104
);
u32
stat
=
nv_rd32
(
gpio
,
0x001144
)
&
intr
;
u32
hi
=
(
intr
&
0x0000ffff
)
>>
0
;
*
lo
=
(
stat
&
0xffff0000
)
>>
16
;
u32
lo
=
(
intr
&
0xffff0000
)
>>
16
;
*
hi
=
(
stat
&
0x0000ffff
);
int
i
;
nv_wr32
(
gpio
,
0x001104
,
intr
);
for
(
i
=
0
;
(
hi
|
lo
)
&&
i
<
32
;
i
++
)
{
if
((
hi
|
lo
)
&
(
1
<<
i
))
nouveau_event_trigger
(
priv
->
base
.
events
,
1
,
i
);
}
nv_wr32
(
priv
,
0x001104
,
intr
);
}
static
void
nv10_gpio_intr_enable
(
struct
nouveau_event
*
event
,
int
line
)
{
nv_wr32
(
event
->
priv
,
0x001104
,
0x00010001
<<
line
);
nv_mask
(
event
->
priv
,
0x001144
,
0x00010001
<<
line
,
0x00010001
<<
line
);
}
}
static
void
static
void
nv10_gpio_intr_
disable
(
struct
nouveau_event
*
event
,
int
line
)
nv10_gpio_intr_
mask
(
struct
nouveau_gpio
*
gpio
,
u32
type
,
u32
mask
,
u32
data
)
{
{
nv_wr32
(
event
->
priv
,
0x001104
,
0x00010001
<<
line
);
u32
inte
=
nv_rd32
(
gpio
,
0x001144
);
nv_mask
(
event
->
priv
,
0x001144
,
0x00010001
<<
line
,
0x00000000
);
if
(
type
&
NVKM_GPIO_LO
)
inte
=
(
inte
&
~
(
mask
<<
16
))
|
(
data
<<
16
);
if
(
type
&
NVKM_GPIO_HI
)
inte
=
(
inte
&
~
mask
)
|
data
;
nv_wr32
(
gpio
,
0x001144
,
inte
);
}
}
static
int
static
int
...
@@ -128,10 +118,6 @@ nv10_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
...
@@ -128,10 +118,6 @@ nv10_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv
->
base
.
drive
=
nv10_gpio_drive
;
priv
->
base
.
drive
=
nv10_gpio_drive
;
priv
->
base
.
sense
=
nv10_gpio_sense
;
priv
->
base
.
sense
=
nv10_gpio_sense
;
priv
->
base
.
events
->
priv
=
priv
;
priv
->
base
.
events
->
enable
=
nv10_gpio_intr_enable
;
priv
->
base
.
events
->
disable
=
nv10_gpio_intr_disable
;
nv_subdev
(
priv
)
->
intr
=
nv10_gpio_intr
;
return
0
;
return
0
;
}
}
...
@@ -175,4 +161,6 @@ nv10_gpio_oclass = &(struct nouveau_gpio_impl) {
...
@@ -175,4 +161,6 @@ nv10_gpio_oclass = &(struct nouveau_gpio_impl) {
.
fini
=
nv10_gpio_fini
,
.
fini
=
nv10_gpio_fini
,
},
},
.
lines
=
16
,
.
lines
=
16
,
.
intr_stat
=
nv10_gpio_intr_stat
,
.
intr_mask
=
nv10_gpio_intr_mask
,
}.
base
;
}.
base
;
drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c
View file @
5693c0f2
...
@@ -95,47 +95,25 @@ nv50_gpio_sense(struct nouveau_gpio *gpio, int line)
...
@@ -95,47 +95,25 @@ nv50_gpio_sense(struct nouveau_gpio *gpio, int line)
return
!!
(
nv_rd32
(
gpio
,
reg
)
&
(
4
<<
shift
));
return
!!
(
nv_rd32
(
gpio
,
reg
)
&
(
4
<<
shift
));
}
}
void
static
void
nv50_gpio_intr
(
struct
nouveau_subdev
*
subdev
)
nv50_gpio_intr_stat
(
struct
nouveau_gpio
*
gpio
,
u32
*
hi
,
u32
*
lo
)
{
struct
nv50_gpio_priv
*
priv
=
(
void
*
)
subdev
;
u32
intr0
,
intr1
=
0
;
u32
hi
,
lo
;
int
i
;
intr0
=
nv_rd32
(
priv
,
0xe054
)
&
nv_rd32
(
priv
,
0xe050
);
if
(
nv_device
(
priv
)
->
chipset
>
0x92
)
intr1
=
nv_rd32
(
priv
,
0xe074
)
&
nv_rd32
(
priv
,
0xe070
);
hi
=
(
intr0
&
0x0000ffff
)
|
(
intr1
<<
16
);
lo
=
(
intr0
>>
16
)
|
(
intr1
&
0xffff0000
);
for
(
i
=
0
;
(
hi
|
lo
)
&&
i
<
32
;
i
++
)
{
if
((
hi
|
lo
)
&
(
1
<<
i
))
nouveau_event_trigger
(
priv
->
base
.
events
,
1
,
i
);
}
nv_wr32
(
priv
,
0xe054
,
intr0
);
if
(
nv_device
(
priv
)
->
chipset
>
0x92
)
nv_wr32
(
priv
,
0xe074
,
intr1
);
}
void
nv50_gpio_intr_enable
(
struct
nouveau_event
*
event
,
int
line
)
{
{
const
u32
addr
=
line
<
16
?
0xe050
:
0xe070
;
u32
intr
=
nv_rd32
(
gpio
,
0x00e054
);
const
u32
mask
=
0x00010001
<<
(
line
&
0xf
);
u32
stat
=
nv_rd32
(
gpio
,
0x00e050
)
&
intr
;
nv_wr32
(
event
->
priv
,
addr
+
0x04
,
mask
);
*
lo
=
(
stat
&
0xffff0000
)
>>
16
;
nv_mask
(
event
->
priv
,
addr
+
0x00
,
mask
,
mask
);
*
hi
=
(
stat
&
0x0000ffff
);
nv_wr32
(
gpio
,
0x00e054
,
intr
);
}
}
void
static
void
nv50_gpio_intr_
disable
(
struct
nouveau_event
*
event
,
int
line
)
nv50_gpio_intr_
mask
(
struct
nouveau_gpio
*
gpio
,
u32
type
,
u32
mask
,
u32
data
)
{
{
const
u32
addr
=
line
<
16
?
0xe050
:
0xe070
;
u32
inte
=
nv_rd32
(
gpio
,
0x00e050
);
const
u32
mask
=
0x00010001
<<
(
line
&
0xf
);
if
(
type
&
NVKM_GPIO_LO
)
nv_wr32
(
event
->
priv
,
addr
+
0x04
,
mask
);
inte
=
(
inte
&
~
(
mask
<<
16
))
|
(
data
<<
16
);
nv_mask
(
event
->
priv
,
addr
+
0x00
,
mask
,
0x00000000
);
if
(
type
&
NVKM_GPIO_HI
)
inte
=
(
inte
&
~
mask
)
|
data
;
nv_wr32
(
gpio
,
0x00e050
,
inte
);
}
}
int
int
...
@@ -154,10 +132,6 @@ nv50_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
...
@@ -154,10 +132,6 @@ nv50_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv
->
base
.
reset
=
nv50_gpio_reset
;
priv
->
base
.
reset
=
nv50_gpio_reset
;
priv
->
base
.
drive
=
nv50_gpio_drive
;
priv
->
base
.
drive
=
nv50_gpio_drive
;
priv
->
base
.
sense
=
nv50_gpio_sense
;
priv
->
base
.
sense
=
nv50_gpio_sense
;
priv
->
base
.
events
->
priv
=
priv
;
priv
->
base
.
events
->
enable
=
nv50_gpio_intr_enable
;
priv
->
base
.
events
->
disable
=
nv50_gpio_intr_disable
;
nv_subdev
(
priv
)
->
intr
=
nv50_gpio_intr
;
return
0
;
return
0
;
}
}
...
@@ -208,5 +182,7 @@ nv50_gpio_oclass = &(struct nouveau_gpio_impl) {
...
@@ -208,5 +182,7 @@ nv50_gpio_oclass = &(struct nouveau_gpio_impl) {
.
init
=
nv50_gpio_init
,
.
init
=
nv50_gpio_init
,
.
fini
=
nv50_gpio_fini
,
.
fini
=
nv50_gpio_fini
,
},
},
.
lines
=
16
.
.
lines
=
16
,
.
intr_stat
=
nv50_gpio_intr_stat
,
.
intr_mask
=
nv50_gpio_intr_mask
,
}.
base
;
}.
base
;
drivers/gpu/drm/nouveau/core/subdev/gpio/nv92.c
View file @
5693c0f2
...
@@ -24,6 +24,38 @@
...
@@ -24,6 +24,38 @@
#include "priv.h"
#include "priv.h"
void
nv92_gpio_intr_stat
(
struct
nouveau_gpio
*
gpio
,
u32
*
hi
,
u32
*
lo
)
{
u32
intr0
=
nv_rd32
(
gpio
,
0x00e054
);
u32
intr1
=
nv_rd32
(
gpio
,
0x00e074
);
u32
stat0
=
nv_rd32
(
gpio
,
0x00e050
)
&
intr0
;
u32
stat1
=
nv_rd32
(
gpio
,
0x00e070
)
&
intr1
;
*
lo
=
(
stat1
&
0xffff0000
)
|
(
stat0
>>
16
);
*
hi
=
(
stat1
<<
16
)
|
(
stat0
&
0x0000ffff
);
nv_wr32
(
gpio
,
0x00e054
,
intr0
);
nv_wr32
(
gpio
,
0x00e074
,
intr1
);
}
void
nv92_gpio_intr_mask
(
struct
nouveau_gpio
*
gpio
,
u32
type
,
u32
mask
,
u32
data
)
{
u32
inte0
=
nv_rd32
(
gpio
,
0x00e050
);
u32
inte1
=
nv_rd32
(
gpio
,
0x00e070
);
if
(
type
&
NVKM_GPIO_LO
)
inte0
=
(
inte0
&
~
(
mask
<<
16
))
|
(
data
<<
16
);
if
(
type
&
NVKM_GPIO_HI
)
inte0
=
(
inte0
&
~
(
mask
&
0xffff
))
|
(
data
&
0xffff
);
mask
>>=
16
;
data
>>=
16
;
if
(
type
&
NVKM_GPIO_LO
)
inte1
=
(
inte1
&
~
(
mask
<<
16
))
|
(
data
<<
16
);
if
(
type
&
NVKM_GPIO_HI
)
inte1
=
(
inte1
&
~
mask
)
|
data
;
nv_wr32
(
gpio
,
0x00e050
,
inte0
);
nv_wr32
(
gpio
,
0x00e070
,
inte1
);
}
struct
nouveau_oclass
*
struct
nouveau_oclass
*
nv92_gpio_oclass
=
&
(
struct
nouveau_gpio_impl
)
{
nv92_gpio_oclass
=
&
(
struct
nouveau_gpio_impl
)
{
.
base
.
handle
=
NV_SUBDEV
(
GPIO
,
0x92
),
.
base
.
handle
=
NV_SUBDEV
(
GPIO
,
0x92
),
...
@@ -33,5 +65,7 @@ nv92_gpio_oclass = &(struct nouveau_gpio_impl) {
...
@@ -33,5 +65,7 @@ nv92_gpio_oclass = &(struct nouveau_gpio_impl) {
.
init
=
nv50_gpio_init
,
.
init
=
nv50_gpio_init
,
.
fini
=
nv50_gpio_fini
,
.
fini
=
nv50_gpio_fini
,
},
},
.
lines
=
32
.
.
lines
=
32
,
.
intr_stat
=
nv92_gpio_intr_stat
,
.
intr_mask
=
nv92_gpio_intr_mask
,
}.
base
;
}.
base
;
drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c
View file @
5693c0f2
...
@@ -88,10 +88,6 @@ nvd0_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
...
@@ -88,10 +88,6 @@ nvd0_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv
->
base
.
reset
=
nvd0_gpio_reset
;
priv
->
base
.
reset
=
nvd0_gpio_reset
;
priv
->
base
.
drive
=
nvd0_gpio_drive
;
priv
->
base
.
drive
=
nvd0_gpio_drive
;
priv
->
base
.
sense
=
nvd0_gpio_sense
;
priv
->
base
.
sense
=
nvd0_gpio_sense
;
priv
->
base
.
events
->
priv
=
priv
;
priv
->
base
.
events
->
enable
=
nv50_gpio_intr_enable
;
priv
->
base
.
events
->
disable
=
nv50_gpio_intr_disable
;
nv_subdev
(
priv
)
->
intr
=
nv50_gpio_intr
;
return
0
;
return
0
;
}
}
...
@@ -105,4 +101,6 @@ nvd0_gpio_oclass = &(struct nouveau_gpio_impl) {
...
@@ -105,4 +101,6 @@ nvd0_gpio_oclass = &(struct nouveau_gpio_impl) {
.
fini
=
nv50_gpio_fini
,
.
fini
=
nv50_gpio_fini
,
},
},
.
lines
=
32
,
.
lines
=
32
,
.
intr_stat
=
nv92_gpio_intr_stat
,
.
intr_mask
=
nv92_gpio_intr_mask
,
}.
base
;
}.
base
;
drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c
View file @
5693c0f2
...
@@ -28,41 +28,36 @@ struct nve0_gpio_priv {
...
@@ -28,41 +28,36 @@ struct nve0_gpio_priv {
struct
nouveau_gpio
base
;
struct
nouveau_gpio
base
;
};
};
void
static
void
nve0_gpio_intr
(
struct
nouveau_subdev
*
subdev
)
nve0_gpio_intr_stat
(
struct
nouveau_gpio
*
gpio
,
u32
*
hi
,
u32
*
lo
)
{
struct
nve0_gpio_priv
*
priv
=
(
void
*
)
subdev
;
u32
intr0
=
nv_rd32
(
priv
,
0xdc00
)
&
nv_rd32
(
priv
,
0xdc08
);
u32
intr1
=
nv_rd32
(
priv
,
0xdc80
)
&
nv_rd32
(
priv
,
0xdc88
);
u32
hi
=
(
intr0
&
0x0000ffff
)
|
(
intr1
<<
16
);
u32
lo
=
(
intr0
>>
16
)
|
(
intr1
&
0xffff0000
);
int
i
;
for
(
i
=
0
;
(
hi
|
lo
)
&&
i
<
32
;
i
++
)
{
if
((
hi
|
lo
)
&
(
1
<<
i
))
nouveau_event_trigger
(
priv
->
base
.
events
,
1
,
i
);
}
nv_wr32
(
priv
,
0xdc00
,
intr0
);
nv_wr32
(
priv
,
0xdc80
,
intr1
);
}
void
nve0_gpio_intr_enable
(
struct
nouveau_event
*
event
,
int
line
)
{
{
const
u32
addr
=
line
<
16
?
0xdc00
:
0xdc80
;
u32
intr0
=
nv_rd32
(
gpio
,
0x00dc00
);
const
u32
mask
=
0x00010001
<<
(
line
&
0xf
);
u32
intr1
=
nv_rd32
(
gpio
,
0x00dc80
);
nv_wr32
(
event
->
priv
,
addr
+
0x00
,
mask
);
u32
stat0
=
nv_rd32
(
gpio
,
0x00dc08
)
&
intr0
;
nv_mask
(
event
->
priv
,
addr
+
0x08
,
mask
,
mask
);
u32
stat1
=
nv_rd32
(
gpio
,
0x00dc88
)
&
intr1
;
*
lo
=
(
stat1
&
0xffff0000
)
|
(
stat0
>>
16
);
*
hi
=
(
stat1
<<
16
)
|
(
stat0
&
0x0000ffff
);
nv_wr32
(
gpio
,
0x00dc00
,
intr0
);
nv_wr32
(
gpio
,
0x00dc80
,
intr1
);
}
}
void
void
nve0_gpio_intr_
disable
(
struct
nouveau_event
*
event
,
int
line
)
nve0_gpio_intr_
mask
(
struct
nouveau_gpio
*
gpio
,
u32
type
,
u32
mask
,
u32
data
)
{
{
const
u32
addr
=
line
<
16
?
0xdc00
:
0xdc80
;
u32
inte0
=
nv_rd32
(
gpio
,
0x00dc08
);
const
u32
mask
=
0x00010001
<<
(
line
&
0xf
);
u32
inte1
=
nv_rd32
(
gpio
,
0x00dc88
);
nv_mask
(
event
->
priv
,
addr
+
0x08
,
mask
,
0x00000000
);
if
(
type
&
NVKM_GPIO_LO
)
nv_wr32
(
event
->
priv
,
addr
+
0x00
,
mask
);
inte0
=
(
inte0
&
~
(
mask
<<
16
))
|
(
data
<<
16
);
if
(
type
&
NVKM_GPIO_HI
)
inte0
=
(
inte0
&
~
(
mask
&
0xffff
))
|
(
data
&
0xffff
);
mask
>>=
16
;
data
>>=
16
;
if
(
type
&
NVKM_GPIO_LO
)
inte1
=
(
inte1
&
~
(
mask
<<
16
))
|
(
data
<<
16
);
if
(
type
&
NVKM_GPIO_HI
)
inte1
=
(
inte1
&
~
mask
)
|
data
;
nv_wr32
(
gpio
,
0x00dc08
,
inte0
);
nv_wr32
(
gpio
,
0x00dc88
,
inte1
);
}
}
int
int
...
@@ -112,10 +107,6 @@ nve0_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
...
@@ -112,10 +107,6 @@ nve0_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv
->
base
.
reset
=
nvd0_gpio_reset
;
priv
->
base
.
reset
=
nvd0_gpio_reset
;
priv
->
base
.
drive
=
nvd0_gpio_drive
;
priv
->
base
.
drive
=
nvd0_gpio_drive
;
priv
->
base
.
sense
=
nvd0_gpio_sense
;
priv
->
base
.
sense
=
nvd0_gpio_sense
;
priv
->
base
.
events
->
priv
=
priv
;
priv
->
base
.
events
->
enable
=
nve0_gpio_intr_enable
;
priv
->
base
.
events
->
disable
=
nve0_gpio_intr_disable
;
nv_subdev
(
priv
)
->
intr
=
nve0_gpio_intr
;
return
0
;
return
0
;
}
}
...
@@ -129,4 +120,6 @@ nve0_gpio_oclass = &(struct nouveau_gpio_impl) {
...
@@ -129,4 +120,6 @@ nve0_gpio_oclass = &(struct nouveau_gpio_impl) {
.
fini
=
nve0_gpio_fini
,
.
fini
=
nve0_gpio_fini
,
},
},
.
lines
=
32
,
.
lines
=
32
,
.
intr_stat
=
nve0_gpio_intr_stat
,
.
intr_mask
=
nve0_gpio_intr_mask
,
}.
base
;
}.
base
;
drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h
View file @
5693c0f2
...
@@ -23,18 +23,35 @@ int nv50_gpio_ctor(struct nouveau_object *, struct nouveau_object *,
...
@@ -23,18 +23,35 @@ int nv50_gpio_ctor(struct nouveau_object *, struct nouveau_object *,
void
nv50_gpio_dtor
(
struct
nouveau_object
*
);
void
nv50_gpio_dtor
(
struct
nouveau_object
*
);
int
nv50_gpio_init
(
struct
nouveau_object
*
);
int
nv50_gpio_init
(
struct
nouveau_object
*
);
int
nv50_gpio_fini
(
struct
nouveau_object
*
,
bool
);
int
nv50_gpio_fini
(
struct
nouveau_object
*
,
bool
);
void
nv50_gpio_intr
(
struct
nouveau_subdev
*
);
void
nv50_gpio_intr_enable
(
struct
nouveau_event
*
,
int
line
);
void
nv50_gpio_intr_disable
(
struct
nouveau_event
*
,
int
line
);
void
nvd0_gpio_reset
(
struct
nouveau_gpio
*
,
u8
);
void
nvd0_gpio_reset
(
struct
nouveau_gpio
*
,
u8
);
int
nvd0_gpio_drive
(
struct
nouveau_gpio
*
,
int
,
int
,
int
);
int
nvd0_gpio_drive
(
struct
nouveau_gpio
*
,
int
,
int
,
int
);
int
nvd0_gpio_sense
(
struct
nouveau_gpio
*
,
int
);
int
nvd0_gpio_sense
(
struct
nouveau_gpio
*
,
int
);
enum
nvkm_gpio_event
{
NVKM_GPIO_HI
=
1
,
NVKM_GPIO_LO
=
2
,
NVKM_GPIO_TOGGLED
=
(
NVKM_GPIO_HI
|
NVKM_GPIO_LO
),
};
struct
nouveau_gpio_impl
{
struct
nouveau_gpio_impl
{
struct
nouveau_oclass
base
;
struct
nouveau_oclass
base
;
int
lines
;
int
lines
;
/* read and ack pending interrupts, returning only data
* for lines that have not been masked off, while still
* performing the ack for anything that was pending.
*/
void
(
*
intr_stat
)(
struct
nouveau_gpio
*
,
u32
*
,
u32
*
);
/* mask on/off interrupts for hi/lo transitions on a
* given set of gpio lines
*/
void
(
*
intr_mask
)(
struct
nouveau_gpio
*
,
u32
,
u32
,
u32
);
};
};
void
nv92_gpio_intr_stat
(
struct
nouveau_gpio
*
,
u32
*
,
u32
*
);
void
nv92_gpio_intr_mask
(
struct
nouveau_gpio
*
,
u32
,
u32
,
u32
);
#endif
#endif
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