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Commit 57d31ffa authored by Tony Lindgren's avatar Tony Lindgren Committed by Russell King
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[ARM PATCH] 2165/1: OMAP update 4/X: Replace 1610 and 5912 header files with 16xx 

Patch from Tony Lindgren

This patch replaces old OMAP headers for 1610 and 5912. These
headers are replaced with a common omap16xx.h header file.

Signed-off-by: Tony Lindgren
parent cc0c832f
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Showing with 71 additions and 133 deletions
include/asm-arm/arch-omap/omap1610.h → include/asm-arm/arch-omap/omap16xx.h
View file @ 57d31ffa
/* linux/include/asm-arm/arch-omap/omap1610.h /* linux/include/asm-arm/arch-omap/omap16xx.h
* *
* Hardware definitions for TI OMAP1610 processor. * Hardware definitions for TI OMAP1610/5912/1710 processors.
* *
* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
* *
...@@ -25,8 +25,8 @@ ...@@ -25,8 +25,8 @@
* 675 Mass Ave, Cambridge, MA 02139, USA. * 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#ifndef __ASM_ARCH_OMAP1610_H #ifndef __ASM_ARCH_OMAP16XX_H
#define __ASM_ARCH_OMAP1610_H #define __ASM_ARCH_OMAP16XX_H
/* /*
* ---------------------------------------------------------------------------- * ----------------------------------------------------------------------------
...@@ -36,17 +36,18 @@ ...@@ -36,17 +36,18 @@
/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
#define OMAP1610_SRAM_BASE 0xD0000000 #define OMAP16XX_SRAM_BASE 0xD0000000
#define OMAP1610_SRAM_SIZE (SZ_16K) #define OMAP1610_SRAM_SIZE (SZ_16K)
#define OMAP1610_SRAM_START 0x20000000 #define OMAP5912_SRAM_SIZE 0x3E800
#define OMAP16XX_SRAM_START 0x20000000
#define OMAP1610_DSP_BASE 0xE0000000 #define OMAP16XX_DSP_BASE 0xE0000000
#define OMAP1610_DSP_SIZE 0x28000 #define OMAP16XX_DSP_SIZE 0x28000
#define OMAP1610_DSP_START 0xE0000000 #define OMAP16XX_DSP_START 0xE0000000
#define OMAP1610_DSPREG_BASE 0xE1000000 #define OMAP16XX_DSPREG_BASE 0xE1000000
#define OMAP1610_DSPREG_SIZE SZ_128K #define OMAP16XX_DSPREG_SIZE SZ_128K
#define OMAP1610_DSPREG_START 0xE1000000 #define OMAP16XX_DSPREG_START 0xE1000000
/* /*
* ---------------------------------------------------------------------------- * ----------------------------------------------------------------------------
...@@ -54,7 +55,8 @@ ...@@ -54,7 +55,8 @@
* ---------------------------------------------------------------------------- * ----------------------------------------------------------------------------
*/ */
#define OMAP1610_SRAM_IDLE_SUSPEND (OMAP1610_SRAM_BASE + OMAP1610_SRAM_SIZE - 0x200) #define OMAP1610_SRAM_IDLE_SUSPEND (OMAP16XX_SRAM_BASE + OMAP1610_SRAM_SIZE - 0x200)
#define OMAP5912_SRAM_IDLE_SUSPEND (OMAP16XX_SRAM_BASE + OMAP5912_SRAM_SIZE - 0x200)
#define OMAP1610_SRAM_API_SUSPEND (OMAP1610_SRAM_IDLE_SUSPEND + 0x100) #define OMAP1610_SRAM_API_SUSPEND (OMAP1610_SRAM_IDLE_SUSPEND + 0x100)
/* /*
...@@ -104,18 +106,18 @@ ...@@ -104,18 +106,18 @@
* Clocks * Clocks
* ---------------------------------------------------------------------------- * ----------------------------------------------------------------------------
*/ */
#define OMAP1610_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) #define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
/* /*
* ---------------------------------------------------------------------------- * ----------------------------------------------------------------------------
* Pin configuration registers * Pin configuration registers
* ---------------------------------------------------------------------------- * ----------------------------------------------------------------------------
*/ */
#define OMAP1610_CONF_VOLTAGE_VDDSHV6 (1 << 8) #define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
#define OMAP1610_CONF_VOLTAGE_VDDSHV7 (1 << 9) #define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
#define OMAP1610_CONF_VOLTAGE_VDDSHV8 (1 << 10) #define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
#define OMAP1610_CONF_VOLTAGE_VDDSHV9 (1 << 11) #define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
#define OMAP1610_SUBLVDS_CONF_VALID (1 << 13) #define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
/* /*
* --------------------------------------------------------------------------- * ---------------------------------------------------------------------------
...@@ -123,7 +125,55 @@ ...@@ -123,7 +125,55 @@
* --------------------------------------------------------------------------- * ---------------------------------------------------------------------------
*/ */
#define TIPB_SWITCH_BASE (0xfffbc800) #define TIPB_SWITCH_BASE (0xfffbc800)
#define OMAP1610_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160) #define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
/* UART3 Registers Maping through MPU bus */
#define UART3_RHR (OMAP_UART3_BASE + 0)
#define UART3_THR (OMAP_UART3_BASE + 0)
#define UART3_DLL (OMAP_UART3_BASE + 0)
#define UART3_IER (OMAP_UART3_BASE + 4)
#define UART3_DLH (OMAP_UART3_BASE + 4)
#define UART3_IIR (OMAP_UART3_BASE + 8)
#define UART3_FCR (OMAP_UART3_BASE + 8)
#define UART3_EFR (OMAP_UART3_BASE + 8)
#define UART3_LCR (OMAP_UART3_BASE + 0x0C)
#define UART3_MCR (OMAP_UART3_BASE + 0x10)
#define UART3_XON1_ADDR1 (OMAP_UART3_BASE + 0x10)
#define UART3_XON2_ADDR2 (OMAP_UART3_BASE + 0x14)
#define UART3_LSR (OMAP_UART3_BASE + 0x14)
#define UART3_TCR (OMAP_UART3_BASE + 0x18)
#define UART3_MSR (OMAP_UART3_BASE + 0x18)
#define UART3_XOFF1 (OMAP_UART3_BASE + 0x18)
#define UART3_XOFF2 (OMAP_UART3_BASE + 0x1C)
#define UART3_SPR (OMAP_UART3_BASE + 0x1C)
#define UART3_TLR (OMAP_UART3_BASE + 0x1C)
#define UART3_MDR1 (OMAP_UART3_BASE + 0x20)
#define UART3_MDR2 (OMAP_UART3_BASE + 0x24)
#define UART3_SFLSR (OMAP_UART3_BASE + 0x28)
#define UART3_TXFLL (OMAP_UART3_BASE + 0x28)
#define UART3_RESUME (OMAP_UART3_BASE + 0x2C)
#define UART3_TXFLH (OMAP_UART3_BASE + 0x2C)
#define UART3_SFREGL (OMAP_UART3_BASE + 0x30)
#define UART3_RXFLL (OMAP_UART3_BASE + 0x30)
#define UART3_SFREGH (OMAP_UART3_BASE + 0x34)
#define UART3_RXFLH (OMAP_UART3_BASE + 0x34)
#define UART3_BLR (OMAP_UART3_BASE + 0x38)
#define UART3_ACREG (OMAP_UART3_BASE + 0x3C)
#define UART3_DIV16 (OMAP_UART3_BASE + 0x3C)
#define UART3_SCR (OMAP_UART3_BASE + 0x40)
#define UART3_SSR (OMAP_UART3_BASE + 0x44)
#define UART3_EBLR (OMAP_UART3_BASE + 0x48)
#define UART3_OSC_12M_SEL (OMAP_UART3_BASE + 0x4C)
#define UART3_MVR (OMAP_UART3_BASE + 0x50)
#endif /* __ASM_ARCH_OMAP1610_H */ /*
* ----------------------------------------------------------------------------
* Pulse-Width Light
* ----------------------------------------------------------------------------
*/
#define OMAP16XX_PWL_BASE (0xfffb5800)
#define OMAP16XX_PWL_ENABLE (OMAP16XX_PWL_BASE + 0x00)
#define OMAP16XX_PWL_CLK_ENABLE (OMAP16XX_PWL_BASE + 0x04)
#endif /* __ASM_ARCH_OMAP16XX_H */
include/asm-arm/arch-omap/omap5912.h deleted 100644 → 0
View file @ cc0c832f
/* linux/include/asm-arm/arch-omap/omap5912.h
*
* Hardware definitions for TI OMAP5912 processor.
*
* Written by Dirk Behme <dirk.behme@de.bosch.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP5912_H
#define __ASM_ARCH_OMAP5912_H
/*
* ----------------------------------------------------------------------------
* Base addresses
* ----------------------------------------------------------------------------
*/
/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
/* OMAP5912 internal SRAM size is 250kByte */
#define OMAP5912_SRAM_BASE 0xD0000000
#define OMAP5912_SRAM_SIZE 0x3E800
#define OMAP5912_SRAM_START 0x20000000
#define OMAP5912_DSP_BASE 0xE0000000
#define OMAP5912_DSP_SIZE 0x50000
#define OMAP5912_DSP_START 0xE0000000
#define OMAP5912_DSPREG_BASE 0xE1000000
#define OMAP5912_DSPREG_SIZE SZ_128K
#define OMAP5912_DSPREG_START 0xE1000000
/*
* ----------------------------------------------------------------------------
* Memory used by power management
* ----------------------------------------------------------------------------
*/
#define OMAP5912_SRAM_IDLE_SUSPEND (OMAP5912_SRAM_BASE + OMAP5912_SRAM_SIZE - 0x200)
#define OMAP5912_SRAM_API_SUSPEND (OMAP5912_SRAM_IDLE_SUSPEND + 0x100)
/*
* ---------------------------------------------------------------------------
* Interrupts
* ---------------------------------------------------------------------------
*/
#define OMAP_IH2_0_BASE (0xfffe0000)
#define OMAP_IH2_1_BASE (0xfffe0100)
#define OMAP_IH2_2_BASE (0xfffe0200)
#define OMAP_IH2_3_BASE (0xfffe0300)
#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
/*
* ----------------------------------------------------------------------------
* System control registers
* ----------------------------------------------------------------------------
*/
#define OMAP5912_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
#endif /* __ASM_ARCH_OMAP5912_H */
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