Commit 582dd5da authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher

drm/amd/pp: implement phm_reset_power_profile_state

mv related code out of force_dpm_level to
phm_reset_power_profile_state
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 29411f05
...@@ -112,26 +112,29 @@ int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level ...@@ -112,26 +112,29 @@ int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level
PHM_FUNC_CHECK(hwmgr); PHM_FUNC_CHECK(hwmgr);
if (hwmgr->hwmgr_func->force_dpm_level != NULL) { if (hwmgr->hwmgr_func->force_dpm_level != NULL)
ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
if (ret)
return ret;
if (hwmgr->hwmgr_func->set_power_profile_state) {
if (hwmgr->current_power_profile == AMD_PP_GFX_PROFILE)
ret = hwmgr->hwmgr_func->set_power_profile_state(
hwmgr,
&hwmgr->gfx_power_profile);
else if (hwmgr->current_power_profile == AMD_PP_COMPUTE_PROFILE)
ret = hwmgr->hwmgr_func->set_power_profile_state(
hwmgr,
&hwmgr->compute_power_profile);
}
}
return ret; return ret;
} }
int phm_reset_power_profile_state(struct pp_hwmgr *hwmgr)
{
int ret = 0;
if (hwmgr->hwmgr_func->set_power_profile_state) {
if (hwmgr->current_power_profile == AMD_PP_GFX_PROFILE)
ret = hwmgr->hwmgr_func->set_power_profile_state(
hwmgr,
&hwmgr->gfx_power_profile);
else if (hwmgr->current_power_profile == AMD_PP_COMPUTE_PROFILE)
ret = hwmgr->hwmgr_func->set_power_profile_state(
hwmgr,
&hwmgr->compute_power_profile);
}
return ret;
}
int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
struct pp_power_state *adjusted_ps, struct pp_power_state *adjusted_ps,
const struct pp_power_state *current_ps) const struct pp_power_state *current_ps)
......
...@@ -245,6 +245,7 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip, ...@@ -245,6 +245,7 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
phm_notify_smc_display_config_after_ps_adjustment(hwmgr); phm_notify_smc_display_config_after_ps_adjustment(hwmgr);
phm_force_dpm_levels(hwmgr, hwmgr->dpm_level); phm_force_dpm_levels(hwmgr, hwmgr->dpm_level);
phm_reset_power_profile_state(hwmgr);
return 0; return 0;
} }
...@@ -437,5 +437,6 @@ extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr, ...@@ -437,5 +437,6 @@ extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks); extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr); extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);
extern int phm_reset_power_profile_state(struct pp_hwmgr *hwmgr);
#endif /* _HARDWARE_MANAGER_H_ */ #endif /* _HARDWARE_MANAGER_H_ */
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