drm/amd/display: Rename trasnform to dpp for dcn's

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dcn10/Makefile

@@ -2,7 +2,7 @@
 # Makefile for DCN.
 
 DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
-		dcn10_transform.o dcn10_opp.o dcn10_timing_generator.o \
+		dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \
 		dcn10_mem_input.o dcn10_mpc.o
 
 AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h → drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h

@@ -22,13 +22,13 @@
  *
  */
 
-#ifndef __DAL_TRANSFORM_DCN10_H__
-#define __DAL_TRANSFORM_DCN10_H__
+#ifndef __DAL_DPP_DCN10_H__
+#define __DAL_DPP_DCN10_H__
 
 #include "transform.h"
 
-#define TO_DCN10_TRANSFORM(transform)\
-	container_of(transform, struct dcn10_transform, base)
+#define TO_DCN10_DPP(transform)\
+	container_of(transform, struct dcn10_dpp, base)
 
 /* TODO: Use correct number of taps. Using polaris values for now */
 #define LB_TOTAL_NUMBER_OF_ENTRIES 5124
@@ -332,15 +332,15 @@
 	type CM_COMB_C33; \
 	type CM_COMB_C34
 
-struct dcn_transform_shift {
+struct dcn_dpp_shift {
 	TF_REG_FIELD_LIST(uint8_t);
 };
 
-struct dcn_transform_mask {
+struct dcn_dpp_mask {
 	TF_REG_FIELD_LIST(uint32_t);
 };
 
-struct dcn_transform_registers {
+struct dcn_dpp_registers {
 	uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT;
 	uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM;
 	uint32_t OTG_H_BLANK;
@@ -395,12 +395,12 @@ struct dcn_transform_registers {
 	uint32_t CM_COMB_C33_C34;
 };
 
-struct dcn10_transform {
+struct dcn10_dpp {
 	struct transform base;
 
-	const struct dcn_transform_registers *tf_regs;
-	const struct dcn_transform_shift *tf_shift;
-	const struct dcn_transform_mask *tf_mask;
+	const struct dcn_dpp_registers *tf_regs;
+	const struct dcn_dpp_shift *tf_shift;
+	const struct dcn_dpp_mask *tf_mask;
 
 	const uint16_t *filter_v;
 	const uint16_t *filter_h;
@@ -410,12 +410,10 @@ struct dcn10_transform {
 	int lb_memory_size;
 	int lb_bits_per_entry;
 };
-
-bool dcn10_transform_construct(struct dcn10_transform *xfmn10,
+bool dcn10_dpp_construct(struct dcn10_dpp *xfm110,
 	struct dc_context *ctx,
 	uint32_t inst,
-	const struct dcn_transform_registers *tf_regs,
-	const struct dcn_transform_shift *tf_shift,
-	const struct dcn_transform_mask *tf_mask);
-
+	const struct dcn_dpp_registers *tf_regs,
+	const struct dcn_dpp_shift *tf_shift,
+	const struct dcn_dpp_mask *tf_mask);
 #endif

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

@@ -33,6 +33,8 @@
 #include "dce110/dce110_hw_sequencer.h"
 #include "dce/dce_hwseq.h"
 #include "abm.h"
+#include "dcn10/dcn10_dpp.h"
+#include "dcn10/dcn10_mpc.h"
 #include "mem_input.h"
 #include "timing_generator.h"
 #include "opp.h"

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

@@ -33,7 +33,7 @@
 #include "dcn10/dcn10_ipp.h"
 #include "dcn10/dcn10_mpc.h"
 #include "irq/dcn10/irq_service_dcn10.h"
-#include "dcn10/dcn10_transform.h"
+#include "dcn10/dcn10_dpp.h"
 #include "dcn10/dcn10_timing_generator.h"
 #include "dcn10/dcn10_hw_sequencer.h"
 #include "dce110/dce110_hw_sequencer.h"
@@ -309,18 +309,18 @@ static const struct dcn10_opp_mask opp_mask = {
 	TF_REG_LIST_DCN10(id),\
 }
 
-static const struct dcn_transform_registers tf_regs[] = {
+static const struct dcn_dpp_registers tf_regs[] = {
 	tf_regs(0),
 	tf_regs(1),
 	tf_regs(2),
 	tf_regs(3),
 };
 
-static const struct dcn_transform_shift tf_shift = {
+static const struct dcn_dpp_shift tf_shift = {
 	TF_REG_LIST_SH_MASK_DCN10(__SHIFT)
 };
 
-static const struct dcn_transform_mask tf_mask = {
+static const struct dcn_dpp_mask tf_mask = {
 	TF_REG_LIST_SH_MASK_DCN10(_MASK),
 };
 
@@ -449,28 +449,28 @@ static const struct dc_debug debug_defaults_diags = {
 #endif
 };
 
-static void dcn10_transform_destroy(struct transform **xfm)
+static void dcn10_dpp_destroy(struct transform **xfm)
 {
-	dm_free(TO_DCN10_TRANSFORM(*xfm));
+	dm_free(TO_DCN10_DPP(*xfm));
 	*xfm = NULL;
 }
 
-static struct transform *dcn10_transform_create(
+static struct transform *dcn10_dpp_create(
 	struct dc_context *ctx,
 	uint32_t inst)
 {
-	struct dcn10_transform *transform =
-		dm_alloc(sizeof(struct dcn10_transform));
+	struct dcn10_dpp *dpp =
+		dm_alloc(sizeof(struct dcn10_dpp));
 
-	if (!transform)
+	if (!dpp)
 		return NULL;
 
-	if (dcn10_transform_construct(transform, ctx, inst,
+	if (dcn10_dpp_construct(dpp, ctx, inst,
 			&tf_regs[inst], &tf_shift, &tf_mask))
-		return &transform->base;
+		return &dpp->base;
 
 	BREAK_TO_DEBUGGER();
-	dm_free(transform);
+	dm_free(dpp);
 	return NULL;
 }
 
@@ -710,7 +710,7 @@ static void destruct(struct dcn10_resource_pool *pool)
 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 
 		if (pool->base.transforms[i] != NULL)
-			dcn10_transform_destroy(&pool->base.transforms[i]);
+			dcn10_dpp_destroy(&pool->base.transforms[i]);
 
 		if (pool->base.ipps[i] != NULL)
 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
@@ -1387,7 +1387,7 @@ static bool construct(
 	#endif
 	}
 
-	/* mem input -> ipp -> transform -> opp -> TG */
+	/* mem input -> ipp -> dpp -> opp -> TG */
 	for (i = 0; i < pool->base.pipe_count; i++) {
 		pool->base.mis[i] = dcn10_mem_input_create(ctx, i);
 		if (pool->base.mis[i] == NULL) {
@@ -1405,12 +1405,12 @@ static bool construct(
 			goto ipp_create_fail;
 		}
 
-		pool->base.transforms[i] = dcn10_transform_create(ctx, i);
+		pool->base.transforms[i] = dcn10_dpp_create(ctx, i);
 		if (pool->base.transforms[i] == NULL) {
 			BREAK_TO_DEBUGGER();
 			dm_error(
-				"DC: failed to create transform!\n");
-			goto transform_create_fail;
+				"DC: failed to create dpp!\n");
+			goto dpp_create_fail;
 		}
 
 		pool->base.opps[i] = dcn10_opp_create(ctx, i);
@@ -1452,7 +1452,7 @@ static bool construct(
 mpcc_create_fail:
 otg_create_fail:
 opp_create_fail:
-transform_create_fail:
+dpp_create_fail:
 ipp_create_fail:
 mi_create_fail:
 irqs_create_fail: