CRIS v32: Add hardware dependent include files and defconfigs for ETRAX FS and ARTPEC-3 chips.

The header files describe the hardware registers available in both
these chips, note that most of this documentation is automatically
generated from the hardware implementation.

include/asm-cris/arch-v32/mach-a3/arbiter.h

+#ifndef _ASM_CRIS_ARCH_ARBITER_H
+#define _ASM_CRIS_ARCH_ARBITER_H
+
+#define EXT_REGION 0
+#define INT_REGION 1
+
+typedef void (watch_callback)(void);
+
+enum {
+	arbiter_all_dmas = 0x7fe,
+	arbiter_cpu = 0x1800,
+	arbiter_all_clients = 0x7fff
+};
+
+enum {
+	arbiter_bar_all_clients = 0x1ff
+};
+
+enum {
+	arbiter_all_read = 0x55,
+	arbiter_all_write = 0xaa,
+	arbiter_all_accesses = 0xff
+};
+
+#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli))
+
+int crisv32_arbiter_allocate_bandwith(int client, int region,
+		unsigned long bandwidth);
+int crisv32_arbiter_watch(unsigned long start, unsigned long size,
+		unsigned long clients, unsigned long accesses,
+		watch_callback * cb);
+int crisv32_arbiter_unwatch(int id);
+
+#endif

include/asm-cris/arch-v32/mach-a3/dma.h

+#ifndef _ASM_ARCH_CRIS_DMA_H
+#define _ASM_ARCH_CRIS_DMA_H
+
+/* Defines for using and allocating dma channels. */
+
+#define MAX_DMA_CHANNELS	12 /* 8 and 10 not used. */
+
+enum dma_owner {
+	dma_eth,
+	dma_ser0,
+	dma_ser1,
+	dma_ser2,
+	dma_ser3,
+	dma_ser4,
+	dma_iop,
+	dma_sser,
+	dma_strp,
+	dma_h264,
+	dma_jpeg
+};
+
+int crisv32_request_dma(unsigned int dmanr, const char *device_id,
+	unsigned options, unsigned bandwidth, enum dma_owner owner);
+void crisv32_free_dma(unsigned int dmanr);
+
+/* Masks used by crisv32_request_dma options: */
+#define DMA_VERBOSE_ON_ERROR 1
+#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
+#define DMA_INT_MEM 4
+
+#endif /* _ASM_ARCH_CRIS_DMA_H */

include/asm-cris/arch-v32/mach-a3/hwregs/asm/clkgen_defs_asm.h

+#ifndef __clkgen_defs_asm_h
+#define __clkgen_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           clkgen.r
+ *
+ *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+	REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+	REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+	REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+	REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+	((inst) + offs + (index) * stride)
+#endif
+
+/* Register r_bootsel, scope clkgen, type r */
+#define reg_clkgen_r_bootsel___boot_mode___lsb 0
+#define reg_clkgen_r_bootsel___boot_mode___width 5
+#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5
+#define reg_clkgen_r_bootsel___intern_main_clk___width 1
+#define reg_clkgen_r_bootsel___intern_main_clk___bit 5
+#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6
+#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1
+#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6
+#define reg_clkgen_r_bootsel_offset 0
+
+/* Register rw_clk_ctrl, scope clkgen, type rw */
+#define reg_clkgen_rw_clk_ctrl___pll___lsb 0
+#define reg_clkgen_rw_clk_ctrl___pll___width 1
+#define reg_clkgen_rw_clk_ctrl___pll___bit 0
+#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1
+#define reg_clkgen_rw_clk_ctrl___cpu___width 1
+#define reg_clkgen_rw_clk_ctrl___cpu___bit 1
+#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2
+#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1
+#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2
+#define reg_clkgen_rw_clk_ctrl___vin___lsb 3
+#define reg_clkgen_rw_clk_ctrl___vin___width 1
+#define reg_clkgen_rw_clk_ctrl___vin___bit 3
+#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4
+#define reg_clkgen_rw_clk_ctrl___sclr___width 1
+#define reg_clkgen_rw_clk_ctrl___sclr___bit 4
+#define reg_clkgen_rw_clk_ctrl___h264___lsb 5
+#define reg_clkgen_rw_clk_ctrl___h264___width 1
+#define reg_clkgen_rw_clk_ctrl___h264___bit 5
+#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6
+#define reg_clkgen_rw_clk_ctrl___ddr2___width 1
+#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6
+#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7
+#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1
+#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7
+#define reg_clkgen_rw_clk_ctrl___eth___lsb 8
+#define reg_clkgen_rw_clk_ctrl___eth___width 1
+#define reg_clkgen_rw_clk_ctrl___eth___bit 8
+#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9
+#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1
+#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9
+#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10
+#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1
+#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10
+#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11
+#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1
+#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11
+#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12
+#define reg_clkgen_rw_clk_ctrl___jpeg___width 1
+#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12
+#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13
+#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1
+#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13
+#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14
+#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1
+#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14
+#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15
+#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1
+#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15
+#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16
+#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1
+#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16
+#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17
+#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1
+#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17
+#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18
+#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1
+#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18
+#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19
+#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1
+#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19
+#define reg_clkgen_rw_clk_ctrl_offset 4
+
+
+/* Constants */
+#define regk_clkgen_eth1000_rx                    0x0000000c
+#define regk_clkgen_eth1000_tx                    0x0000000e
+#define regk_clkgen_eth100_rx                     0x0000001d
+#define regk_clkgen_eth100_rx_half                0x0000001c
+#define regk_clkgen_eth100_tx                     0x0000001f
+#define regk_clkgen_eth100_tx_half                0x0000001e
+#define regk_clkgen_nand_3_2                      0x00000000
+#define regk_clkgen_nand_3_2_0x30                 0x00000002
+#define regk_clkgen_nand_3_2_0x30_pll             0x00000012
+#define regk_clkgen_nand_3_2_pll                  0x00000010
+#define regk_clkgen_nand_3_3                      0x00000001
+#define regk_clkgen_nand_3_3_0x30                 0x00000003
+#define regk_clkgen_nand_3_3_0x30_pll             0x00000013
+#define regk_clkgen_nand_3_3_pll                  0x00000011
+#define regk_clkgen_nand_4_2                      0x00000004
+#define regk_clkgen_nand_4_2_0x30                 0x00000006
+#define regk_clkgen_nand_4_2_0x30_pll             0x00000016
+#define regk_clkgen_nand_4_2_pll                  0x00000014
+#define regk_clkgen_nand_4_3                      0x00000005
+#define regk_clkgen_nand_4_3_0x30                 0x00000007
+#define regk_clkgen_nand_4_3_0x30_pll             0x00000017
+#define regk_clkgen_nand_4_3_pll                  0x00000015
+#define regk_clkgen_nand_5_2                      0x00000008
+#define regk_clkgen_nand_5_2_0x30                 0x0000000a
+#define regk_clkgen_nand_5_2_0x30_pll             0x0000001a
+#define regk_clkgen_nand_5_2_pll                  0x00000018
+#define regk_clkgen_nand_5_3                      0x00000009
+#define regk_clkgen_nand_5_3_0x30                 0x0000000b
+#define regk_clkgen_nand_5_3_0x30_pll             0x0000001b
+#define regk_clkgen_nand_5_3_pll                  0x00000019
+#define regk_clkgen_no                            0x00000000
+#define regk_clkgen_rw_clk_ctrl_default           0x00000002
+#define regk_clkgen_ser                           0x0000000d
+#define regk_clkgen_ser_pll                       0x0000000f
+#define regk_clkgen_yes                           0x00000001
+#endif /* __clkgen_defs_asm_h */

include/asm-cris/arch-v32/mach-a3/hwregs/asm/reg_map_asm.h

+#ifndef __reg_map_asm_h
+#define __reg_map_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:            reg.rmap
+ * 
+ *   by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+#define regi_ccd                                  0xb0000000
+#define regi_ccd_top                              0xb0000000
+#define regi_ccd_dp                               0xb0000400
+#define regi_ccd_stat                             0xb0000800
+#define regi_ccd_tg                               0xb0001000
+#define regi_cfg                                  0xb0002000
+#define regi_clkgen                               0xb0004000
+#define regi_ddr2_ctrl                            0xb0006000
+#define regi_dma0                                 0xb0008000
+#define regi_dma1                                 0xb000a000
+#define regi_dma11                                0xb000c000
+#define regi_dma2                                 0xb000e000
+#define regi_dma3                                 0xb0010000
+#define regi_dma4                                 0xb0012000
+#define regi_dma5                                 0xb0014000
+#define regi_dma6                                 0xb0016000
+#define regi_dma7                                 0xb0018000
+#define regi_dma9                                 0xb001a000
+#define regi_eth                                  0xb001c000
+#define regi_gio                                  0xb0020000
+#define regi_h264                                 0xb0022000
+#define regi_hist                                 0xb0026000
+#define regi_iop                                  0xb0028000
+#define regi_iop_version                          0xb0028000
+#define regi_iop_fifo_in_extra                    0xb0028040
+#define regi_iop_fifo_out_extra                   0xb0028080
+#define regi_iop_trigger_grp0                     0xb00280c0
+#define regi_iop_trigger_grp1                     0xb0028100
+#define regi_iop_trigger_grp2                     0xb0028140
+#define regi_iop_trigger_grp3                     0xb0028180
+#define regi_iop_trigger_grp4                     0xb00281c0
+#define regi_iop_trigger_grp5                     0xb0028200
+#define regi_iop_trigger_grp6                     0xb0028240
+#define regi_iop_trigger_grp7                     0xb0028280
+#define regi_iop_crc_par                          0xb0028300
+#define regi_iop_dmc_in                           0xb0028380
+#define regi_iop_dmc_out                          0xb0028400
+#define regi_iop_fifo_in                          0xb0028480
+#define regi_iop_fifo_out                         0xb0028500
+#define regi_iop_scrc_in                          0xb0028580
+#define regi_iop_scrc_out                         0xb0028600
+#define regi_iop_timer_grp0                       0xb0028680
+#define regi_iop_timer_grp1                       0xb0028700
+#define regi_iop_sap_in                           0xb0028800
+#define regi_iop_sap_out                          0xb0028900
+#define regi_iop_spu                              0xb0028a00
+#define regi_iop_sw_cfg                           0xb0028b00
+#define regi_iop_sw_cpu                           0xb0028c00
+#define regi_iop_sw_mpu                           0xb0028d00
+#define regi_iop_sw_spu                           0xb0028e00
+#define regi_iop_mpu                              0xb0029000
+#define regi_irq                                  0xb002a000
+#define regi_jpeg                                 0xb002c000
+#define regi_l2cache                              0xb0030000
+#define regi_marb_bar                             0xb0032000
+#define regi_marb_bar_bp0                         0xb0032140
+#define regi_marb_bar_bp1                         0xb0032180
+#define regi_marb_bar_bp2                         0xb00321c0
+#define regi_marb_bar_bp3                         0xb0032200
+#define regi_marb_foo                             0xb0034000
+#define regi_marb_foo_bp0                         0xb0034280
+#define regi_marb_foo_bp1                         0xb00342c0
+#define regi_marb_foo_bp2                         0xb0034300
+#define regi_marb_foo_bp3                         0xb0034340
+#define regi_pinmux                               0xb0038000
+#define regi_pio                                  0xb0036000
+#define regi_sclr                                 0xb003a000
+#define regi_sclr_fifo                            0xb003c000
+#define regi_ser0                                 0xb003e000
+#define regi_ser1                                 0xb0040000
+#define regi_ser2                                 0xb0042000
+#define regi_ser3                                 0xb0044000
+#define regi_ser4                                 0xb0046000
+#define regi_sser                                 0xb0048000
+#define regi_strcop                               0xb004a000
+#define regi_strdma0                              0xb004e000
+#define regi_strdma1                              0xb0050000
+#define regi_strdma2                              0xb0052000
+#define regi_strdma3                              0xb0054000
+#define regi_strdma5                              0xb0056000
+#define regi_strmux                               0xb004c000
+#define regi_timer0                               0xb0058000
+#define regi_timer1                               0xb005a000
+#define regi_trace                                0xb005c000
+#define regi_vin                                  0xb005e000
+#define regi_vout                                 0xb0060000
+#endif /* __reg_map_asm_h */

include/asm-cris/arch-v32/mach-a3/hwregs/asm/timer_defs_asm.h

+#ifndef __timer_defs_asm_h
+#define __timer_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           timer.r
+ * 
+ *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_tmr0_div, scope timer, type rw */
+#define reg_timer_rw_tmr0_div_offset 0
+
+/* Register r_tmr0_data, scope timer, type r */
+#define reg_timer_r_tmr0_data_offset 4
+
+/* Register rw_tmr0_ctrl, scope timer, type rw */
+#define reg_timer_rw_tmr0_ctrl___op___lsb 0
+#define reg_timer_rw_tmr0_ctrl___op___width 2
+#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
+#define reg_timer_rw_tmr0_ctrl___freq___width 3
+#define reg_timer_rw_tmr0_ctrl_offset 8
+
+/* Register rw_tmr1_div, scope timer, type rw */
+#define reg_timer_rw_tmr1_div_offset 16
+
+/* Register r_tmr1_data, scope timer, type r */
+#define reg_timer_r_tmr1_data_offset 20
+
+/* Register rw_tmr1_ctrl, scope timer, type rw */
+#define reg_timer_rw_tmr1_ctrl___op___lsb 0
+#define reg_timer_rw_tmr1_ctrl___op___width 2
+#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
+#define reg_timer_rw_tmr1_ctrl___freq___width 3
+#define reg_timer_rw_tmr1_ctrl_offset 24
+
+/* Register rs_cnt_data, scope timer, type rs */
+#define reg_timer_rs_cnt_data___tmr___lsb 0
+#define reg_timer_rs_cnt_data___tmr___width 24
+#define reg_timer_rs_cnt_data___cnt___lsb 24
+#define reg_timer_rs_cnt_data___cnt___width 8
+#define reg_timer_rs_cnt_data_offset 32
+
+/* Register r_cnt_data, scope timer, type r */
+#define reg_timer_r_cnt_data___tmr___lsb 0
+#define reg_timer_r_cnt_data___tmr___width 24
+#define reg_timer_r_cnt_data___cnt___lsb 24
+#define reg_timer_r_cnt_data___cnt___width 8
+#define reg_timer_r_cnt_data_offset 36
+
+/* Register rw_cnt_cfg, scope timer, type rw */
+#define reg_timer_rw_cnt_cfg___clk___lsb 0
+#define reg_timer_rw_cnt_cfg___clk___width 2
+#define reg_timer_rw_cnt_cfg_offset 40
+
+/* Register rw_trig, scope timer, type rw */
+#define reg_timer_rw_trig_offset 48
+
+/* Register rw_trig_cfg, scope timer, type rw */
+#define reg_timer_rw_trig_cfg___tmr___lsb 0
+#define reg_timer_rw_trig_cfg___tmr___width 2
+#define reg_timer_rw_trig_cfg_offset 52
+
+/* Register r_time, scope timer, type r */
+#define reg_timer_r_time_offset 56
+
+/* Register rw_out, scope timer, type rw */
+#define reg_timer_rw_out___tmr___lsb 0
+#define reg_timer_rw_out___tmr___width 2
+#define reg_timer_rw_out_offset 60
+
+/* Register rw_wd_ctrl, scope timer, type rw */
+#define reg_timer_rw_wd_ctrl___cnt___lsb 0
+#define reg_timer_rw_wd_ctrl___cnt___width 8
+#define reg_timer_rw_wd_ctrl___cmd___lsb 8
+#define reg_timer_rw_wd_ctrl___cmd___width 1
+#define reg_timer_rw_wd_ctrl___cmd___bit 8
+#define reg_timer_rw_wd_ctrl___key___lsb 9
+#define reg_timer_rw_wd_ctrl___key___width 7
+#define reg_timer_rw_wd_ctrl_offset 64
+
+/* Register r_wd_stat, scope timer, type r */
+#define reg_timer_r_wd_stat___cnt___lsb 0
+#define reg_timer_r_wd_stat___cnt___width 8
+#define reg_timer_r_wd_stat___cmd___lsb 8
+#define reg_timer_r_wd_stat___cmd___width 1
+#define reg_timer_r_wd_stat___cmd___bit 8
+#define reg_timer_r_wd_stat_offset 68
+
+/* Register rw_intr_mask, scope timer, type rw */
+#define reg_timer_rw_intr_mask___tmr0___lsb 0
+#define reg_timer_rw_intr_mask___tmr0___width 1
+#define reg_timer_rw_intr_mask___tmr0___bit 0
+#define reg_timer_rw_intr_mask___tmr1___lsb 1
+#define reg_timer_rw_intr_mask___tmr1___width 1
+#define reg_timer_rw_intr_mask___tmr1___bit 1
+#define reg_timer_rw_intr_mask___cnt___lsb 2
+#define reg_timer_rw_intr_mask___cnt___width 1
+#define reg_timer_rw_intr_mask___cnt___bit 2
+#define reg_timer_rw_intr_mask___trig___lsb 3
+#define reg_timer_rw_intr_mask___trig___width 1
+#define reg_timer_rw_intr_mask___trig___bit 3
+#define reg_timer_rw_intr_mask_offset 72
+
+/* Register rw_ack_intr, scope timer, type rw */
+#define reg_timer_rw_ack_intr___tmr0___lsb 0
+#define reg_timer_rw_ack_intr___tmr0___width 1
+#define reg_timer_rw_ack_intr___tmr0___bit 0
+#define reg_timer_rw_ack_intr___tmr1___lsb 1
+#define reg_timer_rw_ack_intr___tmr1___width 1
+#define reg_timer_rw_ack_intr___tmr1___bit 1
+#define reg_timer_rw_ack_intr___cnt___lsb 2
+#define reg_timer_rw_ack_intr___cnt___width 1
+#define reg_timer_rw_ack_intr___cnt___bit 2
+#define reg_timer_rw_ack_intr___trig___lsb 3
+#define reg_timer_rw_ack_intr___trig___width 1
+#define reg_timer_rw_ack_intr___trig___bit 3
+#define reg_timer_rw_ack_intr_offset 76
+
+/* Register r_intr, scope timer, type r */
+#define reg_timer_r_intr___tmr0___lsb 0
+#define reg_timer_r_intr___tmr0___width 1
+#define reg_timer_r_intr___tmr0___bit 0
+#define reg_timer_r_intr___tmr1___lsb 1
+#define reg_timer_r_intr___tmr1___width 1
+#define reg_timer_r_intr___tmr1___bit 1
+#define reg_timer_r_intr___cnt___lsb 2
+#define reg_timer_r_intr___cnt___width 1
+#define reg_timer_r_intr___cnt___bit 2
+#define reg_timer_r_intr___trig___lsb 3
+#define reg_timer_r_intr___trig___width 1
+#define reg_timer_r_intr___trig___bit 3
+#define reg_timer_r_intr_offset 80
+
+/* Register r_masked_intr, scope timer, type r */
+#define reg_timer_r_masked_intr___tmr0___lsb 0
+#define reg_timer_r_masked_intr___tmr0___width 1
+#define reg_timer_r_masked_intr___tmr0___bit 0
+#define reg_timer_r_masked_intr___tmr1___lsb 1
+#define reg_timer_r_masked_intr___tmr1___width 1
+#define reg_timer_r_masked_intr___tmr1___bit 1
+#define reg_timer_r_masked_intr___cnt___lsb 2
+#define reg_timer_r_masked_intr___cnt___width 1
+#define reg_timer_r_masked_intr___cnt___bit 2
+#define reg_timer_r_masked_intr___trig___lsb 3
+#define reg_timer_r_masked_intr___trig___width 1
+#define reg_timer_r_masked_intr___trig___bit 3
+#define reg_timer_r_masked_intr_offset 84
+
+/* Register rw_test, scope timer, type rw */
+#define reg_timer_rw_test___dis___lsb 0
+#define reg_timer_rw_test___dis___width 1
+#define reg_timer_rw_test___dis___bit 0
+#define reg_timer_rw_test___en___lsb 1
+#define reg_timer_rw_test___en___width 1
+#define reg_timer_rw_test___en___bit 1
+#define reg_timer_rw_test_offset 88
+
+
+/* Constants */
+#define regk_timer_ext                            0x00000001
+#define regk_timer_f100                           0x00000007
+#define regk_timer_f29_493                        0x00000004
+#define regk_timer_f32                            0x00000005
+#define regk_timer_f32_768                        0x00000006
+#define regk_timer_f90                            0x00000003
+#define regk_timer_hold                           0x00000001
+#define regk_timer_ld                             0x00000000
+#define regk_timer_no                             0x00000000
+#define regk_timer_off                            0x00000000
+#define regk_timer_run                            0x00000002
+#define regk_timer_rw_cnt_cfg_default             0x00000000
+#define regk_timer_rw_intr_mask_default           0x00000000
+#define regk_timer_rw_out_default                 0x00000000
+#define regk_timer_rw_test_default                0x00000000
+#define regk_timer_rw_tmr0_ctrl_default           0x00000000
+#define regk_timer_rw_tmr1_ctrl_default           0x00000000
+#define regk_timer_rw_trig_cfg_default            0x00000000
+#define regk_timer_start                          0x00000001
+#define regk_timer_stop                           0x00000000
+#define regk_timer_time                           0x00000001
+#define regk_timer_tmr0                           0x00000002
+#define regk_timer_tmr1                           0x00000003
+#define regk_timer_vclk                           0x00000002
+#define regk_timer_yes                            0x00000001
+#endif /* __timer_defs_asm_h */

include/asm-cris/arch-v32/mach-a3/hwregs/clkgen_defs.h

+#ifndef __clkgen_defs_h
+#define __clkgen_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           clkgen.r
+ * 
+ *   by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope clkgen */
+
+/* Register r_bootsel, scope clkgen, type r */
+typedef struct {
+  unsigned int boot_mode       : 5;
+  unsigned int intern_main_clk : 1;
+  unsigned int extern_usb2_clk : 1;
+  unsigned int dummy1          : 25;
+} reg_clkgen_r_bootsel;
+#define REG_RD_ADDR_clkgen_r_bootsel 0
+
+/* Register rw_clk_ctrl, scope clkgen, type rw */
+typedef struct {
+  unsigned int pll             : 1;
+  unsigned int cpu             : 1;
+  unsigned int iop_usb         : 1;
+  unsigned int vin             : 1;
+  unsigned int sclr            : 1;
+  unsigned int h264            : 1;
+  unsigned int ddr2            : 1;
+  unsigned int vout_hist       : 1;
+  unsigned int eth             : 1;
+  unsigned int ccd_tg_200      : 1;
+  unsigned int dma0_1_eth      : 1;
+  unsigned int ccd_tg_100      : 1;
+  unsigned int jpeg            : 1;
+  unsigned int sser_ser_dma6_7 : 1;
+  unsigned int strdma0_2_video : 1;
+  unsigned int dma2_3_strcop   : 1;
+  unsigned int dma4_5_iop      : 1;
+  unsigned int dma9_11         : 1;
+  unsigned int memarb_bar_ddr  : 1;
+  unsigned int sclr_h264       : 1;
+  unsigned int dummy1          : 12;
+} reg_clkgen_rw_clk_ctrl;
+#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4
+#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4
+
+
+/* Constants */
+enum {
+  regk_clkgen_eth1000_rx                   = 0x0000000c,
+  regk_clkgen_eth1000_tx                   = 0x0000000e,
+  regk_clkgen_eth100_rx                    = 0x0000001d,
+  regk_clkgen_eth100_rx_half               = 0x0000001c,
+  regk_clkgen_eth100_tx                    = 0x0000001f,
+  regk_clkgen_eth100_tx_half               = 0x0000001e,
+  regk_clkgen_nand_3_2                     = 0x00000000,
+  regk_clkgen_nand_3_2_0x30                = 0x00000002,
+  regk_clkgen_nand_3_2_0x30_pll            = 0x00000012,
+  regk_clkgen_nand_3_2_pll                 = 0x00000010,
+  regk_clkgen_nand_3_3                     = 0x00000001,
+  regk_clkgen_nand_3_3_0x30                = 0x00000003,
+  regk_clkgen_nand_3_3_0x30_pll            = 0x00000013,
+  regk_clkgen_nand_3_3_pll                 = 0x00000011,
+  regk_clkgen_nand_4_2                     = 0x00000004,
+  regk_clkgen_nand_4_2_0x30                = 0x00000006,
+  regk_clkgen_nand_4_2_0x30_pll            = 0x00000016,
+  regk_clkgen_nand_4_2_pll                 = 0x00000014,
+  regk_clkgen_nand_4_3                     = 0x00000005,
+  regk_clkgen_nand_4_3_0x30                = 0x00000007,
+  regk_clkgen_nand_4_3_0x30_pll            = 0x00000017,
+  regk_clkgen_nand_4_3_pll                 = 0x00000015,
+  regk_clkgen_nand_5_2                     = 0x00000008,
+  regk_clkgen_nand_5_2_0x30                = 0x0000000a,
+  regk_clkgen_nand_5_2_0x30_pll            = 0x0000001a,
+  regk_clkgen_nand_5_2_pll                 = 0x00000018,
+  regk_clkgen_nand_5_3                     = 0x00000009,
+  regk_clkgen_nand_5_3_0x30                = 0x0000000b,
+  regk_clkgen_nand_5_3_0x30_pll            = 0x0000001b,
+  regk_clkgen_nand_5_3_pll                 = 0x00000019,
+  regk_clkgen_no                           = 0x00000000,
+  regk_clkgen_rw_clk_ctrl_default          = 0x00000002,
+  regk_clkgen_ser                          = 0x0000000d,
+  regk_clkgen_ser_pll                      = 0x0000000f,
+  regk_clkgen_yes                          = 0x00000001
+};
+#endif /* __clkgen_defs_h */

include/asm-cris/arch-v32/mach-a3/hwregs/ddr2_defs.h

+#ifndef __ddr2_defs_h
+#define __ddr2_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           ddr2.r
+ * 
+ *   by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope ddr2 */
+
+/* Register rw_cfg, scope ddr2, type rw */
+typedef struct {
+  unsigned int col_width        : 4;
+  unsigned int nr_banks         : 1;
+  unsigned int bw               : 1;
+  unsigned int nr_ref           : 4;
+  unsigned int ref_interval     : 11;
+  unsigned int odt_ctrl         : 2;
+  unsigned int odt_mem          : 1;
+  unsigned int imp_strength     : 1;
+  unsigned int auto_imp_cal     : 1;
+  unsigned int imp_cal_override : 1;
+  unsigned int dll_override     : 1;
+  unsigned int dummy1           : 4;
+} reg_ddr2_rw_cfg;
+#define REG_RD_ADDR_ddr2_rw_cfg 0
+#define REG_WR_ADDR_ddr2_rw_cfg 0
+
+/* Register rw_timing, scope ddr2, type rw */
+typedef struct {
+  unsigned int wr  : 3;
+  unsigned int rcd : 3;
+  unsigned int rp  : 3;
+  unsigned int ras : 4;
+  unsigned int rfc : 7;
+  unsigned int rc  : 5;
+  unsigned int rtp : 2;
+  unsigned int rtw : 3;
+  unsigned int wtr : 2;
+} reg_ddr2_rw_timing;
+#define REG_RD_ADDR_ddr2_rw_timing 4
+#define REG_WR_ADDR_ddr2_rw_timing 4
+
+/* Register rw_latency, scope ddr2, type rw */
+typedef struct {
+  unsigned int cas      : 3;
+  unsigned int additive : 3;
+  unsigned int dummy1   : 26;
+} reg_ddr2_rw_latency;
+#define REG_RD_ADDR_ddr2_rw_latency 8
+#define REG_WR_ADDR_ddr2_rw_latency 8
+
+/* Register rw_phy_cfg, scope ddr2, type rw */
+typedef struct {
+  unsigned int en : 1;
+  unsigned int dummy1 : 31;
+} reg_ddr2_rw_phy_cfg;
+#define REG_RD_ADDR_ddr2_rw_phy_cfg 12
+#define REG_WR_ADDR_ddr2_rw_phy_cfg 12
+
+/* Register rw_phy_ctrl, scope ddr2, type rw */
+typedef struct {
+  unsigned int rst       : 1;
+  unsigned int cal_rst   : 1;
+  unsigned int cal_start : 1;
+  unsigned int dummy1    : 29;
+} reg_ddr2_rw_phy_ctrl;
+#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16
+#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16
+
+/* Register rw_ctrl, scope ddr2, type rw */
+typedef struct {
+  unsigned int mrs_data : 16;
+  unsigned int cmd      : 8;
+  unsigned int dummy1   : 8;
+} reg_ddr2_rw_ctrl;
+#define REG_RD_ADDR_ddr2_rw_ctrl 20
+#define REG_WR_ADDR_ddr2_rw_ctrl 20
+
+/* Register rw_pwr_down, scope ddr2, type rw */
+typedef struct {
+  unsigned int self_ref : 2;
+  unsigned int phy_en   : 1;
+  unsigned int dummy1   : 29;
+} reg_ddr2_rw_pwr_down;
+#define REG_RD_ADDR_ddr2_rw_pwr_down 24
+#define REG_WR_ADDR_ddr2_rw_pwr_down 24
+
+/* Register r_stat, scope ddr2, type r */
+typedef struct {
+  unsigned int dll_lock       : 1;
+  unsigned int dll_delay_code : 7;
+  unsigned int imp_cal_done   : 1;
+  unsigned int imp_cal_fault  : 1;
+  unsigned int cal_imp_pu     : 4;
+  unsigned int cal_imp_pd     : 4;
+  unsigned int dummy1         : 14;
+} reg_ddr2_r_stat;
+#define REG_RD_ADDR_ddr2_r_stat 28
+
+/* Register rw_imp_ctrl, scope ddr2, type rw */
+typedef struct {
+  unsigned int imp_pu : 4;
+  unsigned int imp_pd : 4;
+  unsigned int dummy1 : 24;
+} reg_ddr2_rw_imp_ctrl;
+#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32
+#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32
+
+#define STRIDE_ddr2_rw_dll_ctrl 4
+/* Register rw_dll_ctrl, scope ddr2, type rw */
+typedef struct {
+  unsigned int mode      : 1;
+  unsigned int clk_delay : 7;
+  unsigned int dummy1    : 24;
+} reg_ddr2_rw_dll_ctrl;
+#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36
+#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36
+
+#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
+/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
+typedef struct {
+  unsigned int dqs90_delay  : 7;
+  unsigned int dqs180_delay : 7;
+  unsigned int dqs270_delay : 7;
+  unsigned int dqs360_delay : 7;
+  unsigned int dummy1       : 4;
+} reg_ddr2_rw_dqs_dll_ctrl;
+#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52
+#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52
+
+
+/* Constants */
+enum {
+  regk_ddr2_al0                            = 0x00000000,
+  regk_ddr2_al1                            = 0x00000008,
+  regk_ddr2_al2                            = 0x00000010,
+  regk_ddr2_al3                            = 0x00000018,
+  regk_ddr2_al4                            = 0x00000020,
+  regk_ddr2_auto                           = 0x00000003,
+  regk_ddr2_bank4                          = 0x00000000,
+  regk_ddr2_bank8                          = 0x00000001,
+  regk_ddr2_bl4                            = 0x00000002,
+  regk_ddr2_bl8                            = 0x00000003,
+  regk_ddr2_bt_il                          = 0x00000008,
+  regk_ddr2_bt_seq                         = 0x00000000,
+  regk_ddr2_bw16                           = 0x00000001,
+  regk_ddr2_bw32                           = 0x00000000,
+  regk_ddr2_cas2                           = 0x00000020,
+  regk_ddr2_cas3                           = 0x00000030,
+  regk_ddr2_cas4                           = 0x00000040,
+  regk_ddr2_cas5                           = 0x00000050,
+  regk_ddr2_deselect                       = 0x000000c0,
+  regk_ddr2_dic_weak                       = 0x00000002,
+  regk_ddr2_direct                         = 0x00000001,
+  regk_ddr2_dis                            = 0x00000000,
+  regk_ddr2_dll_dis                        = 0x00000001,
+  regk_ddr2_dll_en                         = 0x00000000,
+  regk_ddr2_dll_rst                        = 0x00000100,
+  regk_ddr2_emrs                           = 0x00000081,
+  regk_ddr2_emrs2                          = 0x00000082,
+  regk_ddr2_emrs3                          = 0x00000083,
+  regk_ddr2_full                           = 0x00000001,
+  regk_ddr2_hi_ref_rate                    = 0x00000080,
+  regk_ddr2_mrs                            = 0x00000080,
+  regk_ddr2_no                             = 0x00000000,
+  regk_ddr2_nop                            = 0x000000b8,
+  regk_ddr2_ocd_adj                        = 0x00000200,
+  regk_ddr2_ocd_default                    = 0x00000380,
+  regk_ddr2_ocd_drive0                     = 0x00000100,
+  regk_ddr2_ocd_drive1                     = 0x00000080,
+  regk_ddr2_ocd_exit                       = 0x00000000,
+  regk_ddr2_odt_dis                        = 0x00000000,
+  regk_ddr2_offs                           = 0x00000000,
+  regk_ddr2_pre                            = 0x00000090,
+  regk_ddr2_pre_all                        = 0x00000400,
+  regk_ddr2_pwr_down_fast                  = 0x00000000,
+  regk_ddr2_pwr_down_slow                  = 0x00001000,
+  regk_ddr2_ref                            = 0x00000088,
+  regk_ddr2_rtt150                         = 0x00000040,
+  regk_ddr2_rtt50                          = 0x00000044,
+  regk_ddr2_rtt75                          = 0x00000004,
+  regk_ddr2_rw_cfg_default                 = 0x00186000,
+  regk_ddr2_rw_dll_ctrl_default            = 0x00000000,
+  regk_ddr2_rw_dll_ctrl_size               = 0x00000004,
+  regk_ddr2_rw_dqs_dll_ctrl_default        = 0x00000000,
+  regk_ddr2_rw_dqs_dll_ctrl_size           = 0x00000004,
+  regk_ddr2_rw_latency_default             = 0x00000000,
+  regk_ddr2_rw_phy_cfg_default             = 0x00000000,
+  regk_ddr2_rw_pwr_down_default            = 0x00000000,
+  regk_ddr2_rw_timing_default              = 0x00000000,
+  regk_ddr2_s1Gb                           = 0x0000001a,
+  regk_ddr2_s256Mb                         = 0x0000000f,
+  regk_ddr2_s2Gb                           = 0x00000027,
+  regk_ddr2_s4Gb                           = 0x00000042,
+  regk_ddr2_s512Mb                         = 0x00000015,
+  regk_ddr2_temp0_85                       = 0x00000618,
+  regk_ddr2_temp85_95                      = 0x0000030c,
+  regk_ddr2_term150                        = 0x00000002,
+  regk_ddr2_term50                         = 0x00000003,
+  regk_ddr2_term75                         = 0x00000001,
+  regk_ddr2_test                           = 0x00000080,
+  regk_ddr2_weak                           = 0x00000000,
+  regk_ddr2_wr2                            = 0x00000200,
+  regk_ddr2_wr3                            = 0x00000400,
+  regk_ddr2_yes                            = 0x00000001
+};
+#endif /* __ddr2_defs_h */

include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect.h

+/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr 
+   from intr_vect.r */
+
+#ifndef _INTR_VECT_R
+#define _INTR_VECT_R 
+#define TIMER0_INTR_VECT	0x31
+#define TIMER1_INTR_VECT	0x32
+#define DMA0_INTR_VECT	0x33
+#define DMA1_INTR_VECT	0x34
+#define DMA2_INTR_VECT	0x35
+#define DMA3_INTR_VECT	0x36
+#define DMA4_INTR_VECT	0x37
+#define DMA5_INTR_VECT	0x38
+#define DMA6_INTR_VECT	0x39
+#define DMA7_INTR_VECT	0x3a
+#define DMA9_INTR_VECT	0x3b
+#define DMA11_INTR_VECT	0x3c
+#define GIO_INTR_VECT	0x3d
+#define IOP0_INTR_VECT	0x3e
+#define IOP1_INTR_VECT	0x3f
+#define SER0_INTR_VECT	0x40
+#define SER1_INTR_VECT	0x41
+#define SER2_INTR_VECT	0x42
+#define SER3_INTR_VECT	0x43
+#define SER4_INTR_VECT	0x44
+#define SSER_INTR_VECT	0x45
+#define STRDMA0_INTR_VECT	0x46
+#define STRDMA1_INTR_VECT	0x47
+#define STRDMA2_INTR_VECT	0x48
+#define STRDMA3_INTR_VECT	0x49
+#define STRDMA5_INTR_VECT	0x4a
+#define VIN_INTR_VECT	0x4b
+#define VOUT_INTR_VECT	0x4c
+#define JPEG_INTR_VECT	0x4d
+#define H264_INTR_VECT	0x4e
+#define HISTO_INTR_VECT	0x4f
+#define CCD_INTR_VECT	0x50
+#define ETH_INTR_VECT	0x51
+#define MEMARB_BAR_INTR_VECT	0x52
+#define MEMARB_FOO_INTR_VECT	0x53
+#define PIO_INTR_VECT	0x54
+#define SCLR_INTR_VECT	0x55
+#define SCLR_FIFO_INTR_VECT	0x56
+#define IPI_INTR_VECT   0x57
+#define NBR_INTR_VECT   0x58
+#endif

include/asm-cris/arch-v32/mach-a3/hwregs/intr_vect_defs.h

+#ifndef __intr_vect_defs_h
+#define __intr_vect_defs_h
+
+/*
+ * This file is autogenerated from
+ *   file:           intr_vect.r
+ * 
+ *   by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+  REG_READ( reg_##scope##_##reg, \
+            (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( reg_##scope##_##reg, \
+             (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+	    (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+	     (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+    (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope intr_vect */
+
+
+#define STRIDE_intr_vect_rw_mask 4
+/* Register rw_mask0, scope intr_vect, type rw */
+typedef struct {
+  unsigned int timer0  : 1;
+  unsigned int timer1  : 1;
+  unsigned int dma0    : 1;
+  unsigned int dma1    : 1;
+  unsigned int dma2    : 1;
+  unsigned int dma3    : 1;
+  unsigned int dma4    : 1;
+  unsigned int dma5    : 1;
+  unsigned int dma6    : 1;
+  unsigned int dma7    : 1;
+  unsigned int dma9    : 1;
+  unsigned int dma11   : 1;
+  unsigned int gio     : 1;
+  unsigned int iop0    : 1;
+  unsigned int iop1    : 1;
+  unsigned int ser0    : 1;
+  unsigned int ser1    : 1;
+  unsigned int ser2    : 1;
+  unsigned int ser3    : 1;
+  unsigned int ser4    : 1;
+  unsigned int sser    : 1;
+  unsigned int strdma0 : 1;
+  unsigned int strdma1 : 1;
+  unsigned int strdma2 : 1;
+  unsigned int strdma3 : 1;
+  unsigned int strdma5 : 1;
+  unsigned int vin     : 1;
+  unsigned int vout    : 1;
+  unsigned int jpeg    : 1;
+  unsigned int h264    : 1;
+  unsigned int histo   : 1;
+  unsigned int ccd     : 1;
+} reg_intr_vect_rw_mask0;
+#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0
+#define REG_RD_ADDR_intr_vect_rw_mask 0
+#define REG_WR_ADDR_intr_vect_rw_mask 0
+#define REG_RD_ADDR_intr_vect_rw_mask0 0
+#define REG_WR_ADDR_intr_vect_rw_mask0 0
+
+#define STRIDE_intr_vect_r_vect 4
+/* Register r_vect0, scope intr_vect, type r */
+typedef struct {
+  unsigned int timer0  : 1;
+  unsigned int timer1  : 1;
+  unsigned int dma0    : 1;
+  unsigned int dma1    : 1;
+  unsigned int dma2    : 1;
+  unsigned int dma3    : 1;
+  unsigned int dma4    : 1;
+  unsigned int dma5    : 1;
+  unsigned int dma6    : 1;
+  unsigned int dma7    : 1;
+  unsigned int dma9    : 1;
+  unsigned int dma11   : 1;
+  unsigned int gio     : 1;
+  unsigned int iop0    : 1;
+  unsigned int iop1    : 1;
+  unsigned int ser0    : 1;
+  unsigned int ser1    : 1;
+  unsigned int ser2    : 1;
+  unsigned int ser3    : 1;
+  unsigned int ser4    : 1;
+  unsigned int sser    : 1;
+  unsigned int strdma0 : 1;
+  unsigned int strdma1 : 1;
+  unsigned int strdma2 : 1;
+  unsigned int strdma3 : 1;
+  unsigned int strdma5 : 1;
+  unsigned int vin     : 1;
+  unsigned int vout    : 1;
+  unsigned int jpeg    : 1;
+  unsigned int h264    : 1;
+  unsigned int histo   : 1;
+  unsigned int ccd     : 1;
+} reg_intr_vect_r_vect0;
+#define reg_intr_vect_r_vect reg_intr_vect_r_vect0
+#define REG_RD_ADDR_intr_vect_r_vect 8
+#define REG_RD_ADDR_intr_vect_r_vect0 8
+
+#define STRIDE_intr_vect_r_masked_vect 4
+/* Register r_masked_vect0, scope intr_vect, type r */
+typedef struct {
+  unsigned int timer0  : 1;
+  unsigned int timer1  : 1;
+  unsigned int dma0    : 1;
+  unsigned int dma1    : 1;
+  unsigned int dma2    : 1;
+  unsigned int dma3    : 1;
+  unsigned int dma4    : 1;
+  unsigned int dma5    : 1;
+  unsigned int dma6    : 1;
+  unsigned int dma7    : 1;
+  unsigned int dma9    : 1;
+  unsigned int dma11   : 1;
+  unsigned int gio     : 1;
+  unsigned int iop0    : 1;
+  unsigned int iop1    : 1;
+  unsigned int ser0    : 1;
+  unsigned int ser1    : 1;
+  unsigned int ser2    : 1;
+  unsigned int ser3    : 1;
+  unsigned int ser4    : 1;
+  unsigned int sser    : 1;
+  unsigned int strdma0 : 1;
+  unsigned int strdma1 : 1;
+  unsigned int strdma2 : 1;
+  unsigned int strdma3 : 1;
+  unsigned int strdma5 : 1;
+  unsigned int vin     : 1;
+  unsigned int vout    : 1;
+  unsigned int jpeg    : 1;
+  unsigned int h264    : 1;
+  unsigned int histo   : 1;
+  unsigned int ccd     : 1;
+} reg_intr_vect_r_masked_vect0;
+#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0
+#define REG_RD_ADDR_intr_vect_r_masked_vect0 16
+#define REG_RD_ADDR_intr_vect_r_masked_vect 16
+
+#define STRIDE_intr_vect_rw_xmask 4
+/* Register rw_xmask0, scope intr_vect, type rw */
+typedef struct {
+  unsigned int timer0  : 1;
+  unsigned int timer1  : 1;
+  unsigned int dma0    : 1;
+  unsigned int dma1    : 1;
+  unsigned int dma2    : 1;
+  unsigned int dma3    : 1;
+  unsigned int dma4    : 1;
+  unsigned int dma5    : 1;
+  unsigned int dma6    : 1;
+  unsigned int dma7    : 1;
+  unsigned int dma9    : 1;
+  unsigned int dma11   : 1;
+  unsigned int gio     : 1;
+  unsigned int iop0    : 1;
+  unsigned int iop1    : 1;
+  unsigned int ser0    : 1;
+  unsigned int ser1    : 1;
+  unsigned int ser2    : 1;
+  unsigned int ser3    : 1;
+  unsigned int ser4    : 1;
+  unsigned int sser    : 1;
+  unsigned int strdma0 : 1;
+  unsigned int strdma1 : 1;
+  unsigned int strdma2 : 1;
+  unsigned int strdma3 : 1;
+  unsigned int strdma5 : 1;
+  unsigned int vin     : 1;
+  unsigned int vout    : 1;
+  unsigned int jpeg    : 1;
+  unsigned int h264    : 1;
+  unsigned int histo   : 1;
+  unsigned int ccd     : 1;
+} reg_intr_vect_rw_xmask0;
+#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0
+#define REG_RD_ADDR_intr_vect_rw_xmask0 24
+#define REG_WR_ADDR_intr_vect_rw_xmask0 24
+#define REG_RD_ADDR_intr_vect_rw_xmask 24
+#define REG_WR_ADDR_intr_vect_rw_xmask 24
+
+/* Register rw_mask1, scope intr_vect, type rw */
+typedef struct {
+  unsigned int eth        : 1;
+  unsigned int memarb_bar : 1;
+  unsigned int memarb_foo : 1;
+  unsigned int pio        : 1;
+  unsigned int sclr       : 1;
+  unsigned int sclr_fifo  : 1;
+  unsigned int dummy1     : 26;
+} reg_intr_vect_rw_mask1;
+#define REG_RD_ADDR_intr_vect_rw_mask1 4
+#define REG_WR_ADDR_intr_vect_rw_mask1 4
+
+/* Register r_vect1, scope intr_vect, type r */
+typedef struct {
+  unsigned int eth        : 1;
+  unsigned int memarb_bar : 1;
+  unsigned int memarb_foo : 1;
+  unsigned int pio        : 1;
+  unsigned int sclr       : 1;
+  unsigned int sclr_fifo  : 1;
+  unsigned int dummy1     : 26;
+} reg_intr_vect_r_vect1;
+#define REG_RD_ADDR_intr_vect_r_vect1 12
+
+/* Register r_masked_vect1, scope intr_vect, type r */
+typedef struct {
+  unsigned int eth        : 1;
+  unsigned int memarb_bar : 1;
+  unsigned int memarb_foo : 1;
+  unsigned int pio        : 1;
+  unsigned int sclr       : 1;
+  unsigned int sclr_fifo  : 1;
+  unsigned int dummy1     : 26;
+} reg_intr_vect_r_masked_vect1;
+#define REG_RD_ADDR_intr_vect_r_masked_vect1 20
+
+/* Register rw_xmask1, scope intr_vect, type rw */
+typedef struct {
+  unsigned int eth        : 1;
+  unsigned int memarb_bar : 1;
+  unsigned int memarb_foo : 1;
+  unsigned int pio        : 1;
+  unsigned int sclr       : 1;
+  unsigned int sclr_fifo  : 1;
+  unsigned int dummy1     : 26;
+} reg_intr_vect_rw_xmask1;
+#define REG_RD_ADDR_intr_vect_rw_xmask1 28
+#define REG_WR_ADDR_intr_vect_rw_xmask1 28
+
+/* Register rw_xmask_ctrl, scope intr_vect, type rw */
+typedef struct {
+  unsigned int en : 1;
+  unsigned int dummy1 : 31;
+} reg_intr_vect_rw_xmask_ctrl;
+#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32
+#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32
+
+/* Register r_nmi, scope intr_vect, type r */
+typedef struct {
+  unsigned int watchdog0 : 1;
+  unsigned int watchdog1 : 1;
+  unsigned int dummy1    : 30;
+} reg_intr_vect_r_nmi;
+#define REG_RD_ADDR_intr_vect_r_nmi 64
+
+/* Register r_guru, scope intr_vect, type r */
+typedef struct {
+  unsigned int jtag : 1;
+  unsigned int dummy1 : 31;
+} reg_intr_vect_r_guru;
+#define REG_RD_ADDR_intr_vect_r_guru 68
+
+
+/* Register rw_ipi, scope intr_vect, type rw */
+typedef struct 
+{
+  unsigned int vector;
+} reg_intr_vect_rw_ipi;
+#define REG_RD_ADDR_intr_vect_rw_ipi 72
+#define REG_WR_ADDR_intr_vect_rw_ipi 72
+
+/* Constants */
+enum {
+  regk_intr_vect_no                        = 0x00000000,
+  regk_intr_vect_rw_mask0_default          = 0x00000000,
+  regk_intr_vect_rw_mask1_default          = 0x00000000,
+  regk_intr_vect_rw_xmask0_default         = 0x00000000,
+  regk_intr_vect_rw_xmask1_default         = 0x00000000,
+  regk_intr_vect_rw_xmask_ctrl_default     = 0x00000000,
+  regk_intr_vect_yes                       = 0x00000001
+};
+#endif /* __intr_vect_defs_h */

include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_reg_space_asm.h

+/* Autogenerated Changes here will be lost!
+ * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg 
+ */
+#define iop_version 0
+#define iop_fifo_in_extra 64
+#define iop_fifo_out_extra 128
+#define iop_trigger_grp0 192
+#define iop_trigger_grp1 256
+#define iop_trigger_grp2 320
+#define iop_trigger_grp3 384
+#define iop_trigger_grp4 448
+#define iop_trigger_grp5 512
+#define iop_trigger_grp6 576
+#define iop_trigger_grp7 640
+#define iop_crc_par 768
+#define iop_dmc_in 896
+#define iop_dmc_out 1024
+#define iop_fifo_in 1152
+#define iop_fifo_out 1280
+#define iop_scrc_in 1408
+#define iop_scrc_out 1536
+#define iop_timer_grp0 1664
+#define iop_timer_grp1 1792
+#define iop_sap_in 2048
+#define iop_sap_out 2304
+#define iop_spu 2560
+#define iop_sw_cfg 2816
+#define iop_sw_cpu 3072
+#define iop_sw_mpu 3328
+#define iop_sw_spu 3584
+#define iop_mpu 4096

include/asm-cris/arch-v32/mach-a3/hwregs/iop/asm/iop_sap_in_defs_asm.h

+#ifndef __iop_sap_in_defs_asm_h
+#define __iop_sap_in_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ *   file:           iop_sap_in.r
+ * 
+ *   by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+			 STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+                          ((inst) + offs + (index) * stride)
+#endif
+
+#define STRIDE_iop_sap_in_rw_bus_byte 4
+/* Register rw_bus_byte, scope iop_sap_in, type rw */
+#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0
+#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2
+#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2
+#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3
+#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5
+#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2
+#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7
+#define reg_iop_sap_in_rw_bus_byte___delay___width 2
+#define reg_iop_sap_in_rw_bus_byte_offset 0
+
+#define STRIDE_iop_sap_in_rw_gio 4
+/* Register rw_gio, scope iop_sap_in, type rw */
+#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
+#define reg_iop_sap_in_rw_gio___sync_sel___width 2
+#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
+#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
+#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
+#define reg_iop_sap_in_rw_gio___sync_edge___width 2
+#define reg_iop_sap_in_rw_gio___delay___lsb 7
+#define reg_iop_sap_in_rw_gio___delay___width 2
+#define reg_iop_sap_in_rw_gio___logic___lsb 9
+#define reg_iop_sap_in_rw_gio___logic___width 2
+#define reg_iop_sap_in_rw_gio_offset 16
+
+
+/* Constants */
+#define regk_iop_sap_in_and                       0x00000002
+#define regk_iop_sap_in_ext_clk200                0x00000003
+#define regk_iop_sap_in_gio0                      0x00000000
+#define regk_iop_sap_in_gio12                     0x00000003
+#define regk_iop_sap_in_gio16                     0x00000004
+#define regk_iop_sap_in_gio20                     0x00000005
+#define regk_iop_sap_in_gio24                     0x00000006
+#define regk_iop_sap_in_gio28                     0x00000007
+#define regk_iop_sap_in_gio4                      0x00000001
+#define regk_iop_sap_in_gio8                      0x00000002
+#define regk_iop_sap_in_inv                       0x00000001
+#define regk_iop_sap_in_neg                       0x00000002
+#define regk_iop_sap_in_no                        0x00000000
+#define regk_iop_sap_in_no_del_ext_clk200         0x00000002
+#define regk_iop_sap_in_none                      0x00000000
+#define regk_iop_sap_in_one                       0x00000001
+#define regk_iop_sap_in_or                        0x00000003
+#define regk_iop_sap_in_pos                       0x00000001
+#define regk_iop_sap_in_pos_neg                   0x00000003
+#define regk_iop_sap_in_rw_bus_byte_default       0x00000000
+#define regk_iop_sap_in_rw_bus_byte_size          0x00000004
+#define regk_iop_sap_in_rw_gio_default            0x00000000
+#define regk_iop_sap_in_rw_gio_size               0x00000020
+#define regk_iop_sap_in_timer_grp0_tmr3           0x00000000
+#define regk_iop_sap_in_timer_grp1_tmr3           0x00000001
+#define regk_iop_sap_in_tmr_clk200                0x00000001
+#define regk_iop_sap_in_two                       0x00000002
+#define regk_iop_sap_in_two_clk200                0x00000000
+#endif /* __iop_sap_in_defs_asm_h */