Commit 58f6e632 authored by Chon Ming Lee's avatar Chon Ming Lee Committed by Daniel Vetter

drm/i915: Fix VLV eDP timing v2

Fix the typo in previous commit for DP 1.62 divisor.
drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2

v2: sigh, the m1 div is 3.
Reported-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarChon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 814e9b57
...@@ -59,7 +59,7 @@ static const struct dp_link_dpll pch_dpll[] = { ...@@ -59,7 +59,7 @@ static const struct dp_link_dpll pch_dpll[] = {
static const struct dp_link_dpll vlv_dpll[] = { static const struct dp_link_dpll vlv_dpll[] = {
{ DP_LINK_BW_1_62, { DP_LINK_BW_1_62,
{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } }, { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
{ DP_LINK_BW_2_7, { DP_LINK_BW_2_7,
{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
}; };
......
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