Commit 5a32c854 authored by Antonino Daplas's avatar Antonino Daplas Committed by Linus Torvalds

[PATCH] Updates to rivafb driver

The patch updates rivafb to the following:

1.  Fixed cursor corruption and simplified cursor code.

2.  Maximized var->yres_virtual on initial mode setting.  Scrolling,
   therefore, defaults to y-panning which is significantly faster.

3.  Restricted var->xres_virtual and var->yres_virtual to 0x7fff
   (hardware limitation?).  Otherwise, var->yres_virtual > 0x7fff + panning
   will hang the GPU.

4.  Added I2C/DDC support.  This feature enables independent mode setup
   to rivafb.  'stty rows n cols n' should now work correctly.  This is a
   configurable option.

5. Various/minor fixes to drawing code.
Signed-off-by: default avatarAntonino Daplas <adaplas@pol.net>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 0b0fe5ae
...@@ -432,6 +432,11 @@ config FB_RIVA ...@@ -432,6 +432,11 @@ config FB_RIVA
To compile this driver as a module, choose M here: the To compile this driver as a module, choose M here: the
module will be called rivafb. module will be called rivafb.
config FB_RIVA_I2C
bool "Enable DDC Support"
depends on FB_RIVA && I2C
help
config FB_I810 config FB_I810
tristate "Intel 810/815 support (EXPERIMENTAL)" tristate "Intel 810/815 support (EXPERIMENTAL)"
depends on FB && AGP && AGP_INTEL && EXPERIMENTAL && PCI depends on FB && AGP && AGP_INTEL && EXPERIMENTAL && PCI
......
...@@ -2,6 +2,10 @@ ...@@ -2,6 +2,10 @@
# Makefile for the Riva framebuffer driver # Makefile for the Riva framebuffer driver
# #
obj-$(CONFIG_FB_RIVA) += rivafb.o obj-$(CONFIG_FB_RIVA) += rivafb.o
rivafb-objs := fbdev.o riva_hw.o nv_driver.o rivafb-objs := fbdev.o riva_hw.o nv_driver.o
ifdef CONFIG_FB_RIVA_I2C
rivafb-objs += rivafb-i2c.o
endif
This diff is collapsed.
/*
* linux/drivers/video/riva/fbdev-i2c.c - nVidia i2c
*
* Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
*
* Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
*
* Based on radeonfb-i2c.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/fb.h>
#include <asm/io.h>
#include "rivafb.h"
#include "../edid.h"
#define RIVA_DDC 0x50
static void riva_gpio_setscl(void* data, int state)
{
struct riva_i2c_chan *chan = (struct riva_i2c_chan *)data;
struct riva_par *par = chan->par;
u32 val;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
if (state)
val |= 0x20;
else
val &= ~0x20;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
}
static void riva_gpio_setsda(void* data, int state)
{
struct riva_i2c_chan *chan = (struct riva_i2c_chan *)data;
struct riva_par *par = chan->par;
u32 val;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
if (state)
val |= 0x10;
else
val &= ~0x10;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
}
static int riva_gpio_getscl(void* data)
{
struct riva_i2c_chan *chan = (struct riva_i2c_chan *)data;
struct riva_par *par = chan->par;
u32 val = 0;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x04)
val = 1;
val = VGA_RD08(par->riva.PCIO, 0x3d5);
return val;
}
static int riva_gpio_getsda(void* data)
{
struct riva_i2c_chan *chan = (struct riva_i2c_chan *)data;
struct riva_par *par = chan->par;
u32 val = 0;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x08)
val = 1;
return val;
}
#define I2C_ALGO_RIVA 0x0e0000
static int riva_setup_i2c_bus(struct riva_i2c_chan *chan, const char *name)
{
int rc;
strcpy(chan->adapter.name, name);
chan->adapter.owner = THIS_MODULE;
chan->adapter.id = I2C_ALGO_RIVA;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = &chan->par->pdev->dev;
chan->algo.setsda = riva_gpio_setsda;
chan->algo.setscl = riva_gpio_setscl;
chan->algo.getsda = riva_gpio_getsda;
chan->algo.getscl = riva_gpio_getscl;
chan->algo.udelay = 40;
chan->algo.timeout = 20;
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
/* Raise SCL and SDA */
riva_gpio_setsda(chan, 1);
riva_gpio_setscl(chan, 1);
udelay(20);
rc = i2c_bit_add_bus(&chan->adapter);
if (rc == 0)
dev_dbg(&chan->par->pdev->dev, "I2C bus %s registered.\n", name);
else
dev_warn(&chan->par->pdev->dev, "Failed to register I2C bus %s.\n", name);
return rc;
}
void riva_create_i2c_busses(struct riva_par *par)
{
par->chan[0].par = par;
par->chan[1].par = par;
par->chan[2].par = par;
switch (par->riva.Architecture) {
#if 0 /* no support yet for other nVidia chipsets */
par->chan[2].ddc_base = 0x50;
riva_setup_i2c_bus(&par->chan[2], "BUS2");
#endif
case NV_ARCH_10:
case NV_ARCH_20:
case NV_ARCH_04:
par->chan[1].ddc_base = 0x36;
riva_setup_i2c_bus(&par->chan[1], "BUS1");
case NV_ARCH_03:
par->chan[0].ddc_base = 0x3e;
riva_setup_i2c_bus(&par->chan[0], "BUS0");
}
}
void riva_delete_i2c_busses(struct riva_par *par)
{
if (par->chan[0].par)
i2c_bit_del_bus(&par->chan[0].adapter);
par->chan[0].par = NULL;
if (par->chan[1].par)
i2c_bit_del_bus(&par->chan[1].adapter);
par->chan[1].par = NULL;
}
static u8 *riva_do_probe_i2c_edid(struct riva_i2c_chan *chan)
{
u8 start = 0x0;
struct i2c_msg msgs[] = {
{
.addr = RIVA_DDC,
.len = 1,
.buf = &start,
}, {
.addr = RIVA_DDC,
.flags = I2C_M_RD,
.len = EDID_LENGTH,
},
};
u8 *buf;
buf = kmalloc(EDID_LENGTH, GFP_KERNEL);
if (!buf) {
dev_warn(&chan->par->pdev->dev, "Out of memory!\n");
return NULL;
}
msgs[1].buf = buf;
if (i2c_transfer(&chan->adapter, msgs, 2) == 2)
return buf;
dev_dbg(&chan->par->pdev->dev, "Unable to read EDID block.\n");
kfree(buf);
return NULL;
}
int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid)
{
u8 *edid = NULL;
int i;
for (i = 0; i < 3; i++) {
/* Do the real work */
edid = riva_do_probe_i2c_edid(&par->chan[conn-1]);
if (edid)
break;
}
if (out_edid)
*out_edid = edid;
if (!edid)
return 1;
return 0;
}
...@@ -4,6 +4,10 @@ ...@@ -4,6 +4,10 @@
#include <linux/config.h> #include <linux/config.h>
#include <linux/fb.h> #include <linux/fb.h>
#include <video/vga.h> #include <video/vga.h>
#include <linux/i2c.h>
#include <linux/i2c-id.h>
#include <linux/i2c-algo-bit.h>
#include "riva_hw.h" #include "riva_hw.h"
/* GGI compatibility macros */ /* GGI compatibility macros */
...@@ -12,6 +16,12 @@ ...@@ -12,6 +16,12 @@
#define NUM_GRC_REGS 0x09 #define NUM_GRC_REGS 0x09
#define NUM_ATC_REGS 0x15 #define NUM_ATC_REGS 0x15
/* I2C */
#define DDC_SCL_READ_MASK (1 << 2)
#define DDC_SCL_WRITE_MASK (1 << 5)
#define DDC_SDA_READ_MASK (1 << 3)
#define DDC_SDA_WRITE_MASK (1 << 4)
/* holds the state of the VGA core and extended Riva hw state from riva_hw.c. /* holds the state of the VGA core and extended Riva hw state from riva_hw.c.
* From KGI originally. */ * From KGI originally. */
struct riva_regs { struct riva_regs {
...@@ -23,6 +33,15 @@ struct riva_regs { ...@@ -23,6 +33,15 @@ struct riva_regs {
RIVA_HW_STATE ext; RIVA_HW_STATE ext;
}; };
struct riva_par;
struct riva_i2c_chan {
struct riva_par *par;
unsigned long ddc_base;
struct i2c_adapter adapter;
struct i2c_algo_bit_data algo;
};
struct riva_par { struct riva_par {
RIVA_HW_INST riva; /* interface to riva_hw.c */ RIVA_HW_INST riva; /* interface to riva_hw.c */
...@@ -36,26 +55,22 @@ struct riva_par { ...@@ -36,26 +55,22 @@ struct riva_par {
u32 cursor_data[32 * 32/4]; u32 cursor_data[32 * 32/4];
int cursor_reset; int cursor_reset;
unsigned char *EDID; unsigned char *EDID;
int panel_xres, panel_yres;
int hOver_plus, hSync_width, hblank;
int vOver_plus, vSync_width, vblank;
int hAct_high, vAct_high, interlaced;
int synct, misc, clock;
int use_default_var;
int got_dfpinfo;
unsigned int Chipset; unsigned int Chipset;
int forceCRTC; int forceCRTC;
Bool SecondCRTC; Bool SecondCRTC;
int FlatPanel; int FlatPanel;
struct pci_dev *pdev;
#ifdef CONFIG_MTRR #ifdef CONFIG_MTRR
struct { int vram; int vram_valid; } mtrr; struct { int vram; int vram_valid; } mtrr;
#endif #endif
struct riva_i2c_chan chan[3];
}; };
void riva_common_setup(struct riva_par *); void riva_common_setup(struct riva_par *);
unsigned long riva_get_memlen(struct riva_par *); unsigned long riva_get_memlen(struct riva_par *);
unsigned long riva_get_maxdclk(struct riva_par *); unsigned long riva_get_maxdclk(struct riva_par *);
void riva_delete_i2c_busses(struct riva_par *par);
void riva_create_i2c_busses(struct riva_par *par);
int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid);
#endif /* __RIVAFB_H */ #endif /* __RIVAFB_H */
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