Skip to content

L
linux
Commit 5a4d68e6 authored by David S. Miller's avatar David S. Miller
Browse files
Options

[SPARC64]: Tidy asm macros in sfp-util.h

parent 80fe944f
Hide whitespace changes
Inline Side-by-side
Showing with 90 additions and 90 deletions
arch/sparc64/math-emu/sfp-util.h
View file @ 5a4d68e6
...@@ -11,106 +11,106 @@ ...@@ -11,106 +11,106 @@
#include <linux/types.h> #include <linux/types.h>
#include <asm/byteorder.h> #include <asm/byteorder.h>
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addcc %4,%5,%1\n\ __asm__ ("addcc %4,%5,%1\n\t" \
add %2,%3,%0\n\ "add %2,%3,%0\n\t" \
bcs,a,pn %%xcc, 1f\n\ "bcs,a,pn %%xcc, 1f\n\t" \
add %0, 1, %0\n\ "add %0, 1, %0\n" \
1:" \ "1:" \
: "=r" ((UDItype)(sh)), \ : "=r" ((UDItype)(sh)), \
"=&r" ((UDItype)(sl)) \ "=&r" ((UDItype)(sl)) \
: "r" ((UDItype)(ah)), \ : "r" ((UDItype)(ah)), \
"r" ((UDItype)(bh)), \ "r" ((UDItype)(bh)), \
"r" ((UDItype)(al)), \ "r" ((UDItype)(al)), \
"r" ((UDItype)(bl)) \ "r" ((UDItype)(bl)) \
: "cc") : "cc")
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subcc %4,%5,%1\n\ __asm__ ("subcc %4,%5,%1\n\t" \
sub %2,%3,%0\n\ "sub %2,%3,%0\n\t" \
bcs,a,pn %%xcc, 1f\n\ "bcs,a,pn %%xcc, 1f\n\t" \
sub %0, 1, %0\n\ "sub %0, 1, %0\n" \
1:" \ "1:" \
: "=r" ((UDItype)(sh)), \ : "=r" ((UDItype)(sh)), \
"=&r" ((UDItype)(sl)) \ "=&r" ((UDItype)(sl)) \
: "r" ((UDItype)(ah)), \ : "r" ((UDItype)(ah)), \
"r" ((UDItype)(bh)), \ "r" ((UDItype)(bh)), \
"r" ((UDItype)(al)), \ "r" ((UDItype)(al)), \
"r" ((UDItype)(bl)) \ "r" ((UDItype)(bl)) \
: "cc") : "cc")
#define umul_ppmm(wh, wl, u, v) \ #define umul_ppmm(wh, wl, u, v) \
do { \ do { \
UDItype tmp1, tmp2, tmp3, tmp4; \ UDItype tmp1, tmp2, tmp3, tmp4; \
__asm__ __volatile__ ( \ __asm__ __volatile__ ( \
"srl %7,0,%3\n\ "srl %7,0,%3\n\t" \
mulx %3,%6,%1\n\ "mulx %3,%6,%1\n\t" \
srlx %6,32,%2\n\ "srlx %6,32,%2\n\t" \
mulx %2,%3,%4\n\ "mulx %2,%3,%4\n\t" \
sllx %4,32,%5\n\ "sllx %4,32,%5\n\t" \
srl %6,0,%3\n\ "srl %6,0,%3\n\t" \
sub %1,%5,%5\n\ "sub %1,%5,%5\n\t" \
srlx %5,32,%5\n\ "srlx %5,32,%5\n\t" \
addcc %4,%5,%4\n\ "addcc %4,%5,%4\n\t" \
srlx %7,32,%5\n\ "srlx %7,32,%5\n\t" \
mulx %3,%5,%3\n\ "mulx %3,%5,%3\n\t" \
mulx %2,%5,%5\n\ "mulx %2,%5,%5\n\t" \
sethi %%hi(0x80000000),%2\n\ "sethi %%hi(0x80000000),%2\n\t" \
addcc %4,%3,%4\n\ "addcc %4,%3,%4\n\t" \
srlx %4,32,%4\n\ "srlx %4,32,%4\n\t" \
add %2,%2,%2\n\ "add %2,%2,%2\n\t" \
movcc %%xcc,%%g0,%2\n\ "movcc %%xcc,%%g0,%2\n\t" \
addcc %5,%4,%5\n\ "addcc %5,%4,%5\n\t" \
sllx %3,32,%3\n\ "sllx %3,32,%3\n\t" \
add %1,%3,%1\n\ "add %1,%3,%1\n\t" \
add %5,%2,%0" \ "add %5,%2,%0" \
: "=r" ((UDItype)(wh)), \ : "=r" ((UDItype)(wh)), \
"=&r" ((UDItype)(wl)), \ "=&r" ((UDItype)(wl)), \
"=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \ "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
: "r" ((UDItype)(u)), \ : "r" ((UDItype)(u)), \
"r" ((UDItype)(v)) \ "r" ((UDItype)(v)) \
: "cc"); \ : "cc"); \
} while (0) } while (0)
#define udiv_qrnnd(q, r, n1, n0, d) \ #define udiv_qrnnd(q, r, n1, n0, d) \
do { \ do { \
UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \ UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
__d1 = (d >> 32); \ __d1 = (d >> 32); \
__d0 = (USItype)d; \ __d0 = (USItype)d; \
\ \
__r1 = (n1) % __d1; \ __r1 = (n1) % __d1; \
__q1 = (n1) / __d1; \ __q1 = (n1) / __d1; \
__m = (UWtype) __q1 * __d0; \ __m = (UWtype) __q1 * __d0; \
__r1 = (__r1 << 32) | (n0 >> 32); \ __r1 = (__r1 << 32) | (n0 >> 32); \
if (__r1 < __m) \ if (__r1 < __m) \
{ \ { \
__q1--, __r1 += (d); \ __q1--, __r1 += (d); \
if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */ \ if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */ \
if (__r1 < __m) \ if (__r1 < __m) \
__q1--, __r1 += (d); \ __q1--, __r1 += (d); \
} \ } \
__r1 -= __m; \ __r1 -= __m; \
\ \
__r0 = __r1 % __d1; \ __r0 = __r1 % __d1; \
__q0 = __r1 / __d1; \ __q0 = __r1 / __d1; \
__m = (UWtype) __q0 * __d0; \ __m = (UWtype) __q0 * __d0; \
__r0 = (__r0 << 32) | ((USItype)n0); \ __r0 = (__r0 << 32) | ((USItype)n0); \
if (__r0 < __m) \ if (__r0 < __m) \
{ \ { \
__q0--, __r0 += (d); \ __q0--, __r0 += (d); \
if (__r0 >= (d)) \ if (__r0 >= (d)) \
if (__r0 < __m) \ if (__r0 < __m) \
__q0--, __r0 += (d); \ __q0--, __r0 += (d); \
} \ } \
__r0 -= __m; \ __r0 -= __m; \
\ \
(q) = (UWtype) (__q1 << 32) | __q0; \ (q) = (UWtype) (__q1 << 32) | __q0; \
(r) = __r0; \ (r) = __r0; \
} while (0) } while (0)
#define UDIV_NEEDS_NORMALIZATION 1 #define UDIV_NEEDS_NORMALIZATION 1
#define abort() \ #define abort() \
return 0 return 0
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7