[SPARC64]: Tidy asm macros in sfp-util.h

arch/sparc64/math-emu/sfp-util.h

@@ -12,11 +12,11 @@
 #include <asm/byteorder.h>
 
 #define add_ssaaaa(sh, sl, ah, al, bh, bl) 	\
-  __asm__ ("addcc %4,%5,%1\n\
-  	    add %2,%3,%0\n\
-  	    bcs,a,pn %%xcc, 1f\n\
-  	    add %0, 1, %0\n\
-  	    1:"										\
+  __asm__ ("addcc %4,%5,%1\n\t"			\
+	   "add %2,%3,%0\n\t"			\
+  	   "bcs,a,pn %%xcc, 1f\n\t"		\
+  	   "add %0, 1, %0\n"			\
+  	   "1:"					\
 	   : "=r" ((UDItype)(sh)),		\
 	     "=&r" ((UDItype)(sl))		\
 	   : "r" ((UDItype)(ah)),		\
@@ -26,11 +26,11 @@
 	   : "cc")
 	   
 #define sub_ddmmss(sh, sl, ah, al, bh, bl) 	\
-  __asm__ ("subcc %4,%5,%1\n\
-  	    sub %2,%3,%0\n\
-  	    bcs,a,pn %%xcc, 1f\n\
-  	    sub %0, 1, %0\n\
-  	    1:"										\
+  __asm__ ("subcc %4,%5,%1\n\t"			\
+  	   "sub %2,%3,%0\n\t"			\
+  	   "bcs,a,pn %%xcc, 1f\n\t"		\
+  	   "sub %0, 1, %0\n"			\
+  	   "1:"					\
 	   : "=r" ((UDItype)(sh)),		\
 	     "=&r" ((UDItype)(sl))		\
 	   : "r" ((UDItype)(ah)),		\
@@ -43,27 +43,27 @@
   do {							\
 	  UDItype tmp1, tmp2, tmp3, tmp4;		\
 	  __asm__ __volatile__ (			\
-		   "srl %7,0,%3\n\
-		    mulx %3,%6,%1\n\
-		    srlx %6,32,%2\n\
-		    mulx %2,%3,%4\n\
-		    sllx %4,32,%5\n\
-		    srl %6,0,%3\n\
-		    sub %1,%5,%5\n\
-		    srlx %5,32,%5\n\
-		    addcc %4,%5,%4\n\
-		    srlx %7,32,%5\n\
-		    mulx %3,%5,%3\n\
-		    mulx %2,%5,%5\n\
-		    sethi %%hi(0x80000000),%2\n\
-		    addcc %4,%3,%4\n\
-		    srlx %4,32,%4\n\
-		    add %2,%2,%2\n\
-		    movcc %%xcc,%%g0,%2\n\
-		    addcc %5,%4,%5\n\
-		    sllx %3,32,%3\n\
-		    add %1,%3,%1\n\
-		    add %5,%2,%0"							\
+		   "srl %7,0,%3\n\t"			\
+		   "mulx %3,%6,%1\n\t"			\
+		   "srlx %6,32,%2\n\t"			\
+		   "mulx %2,%3,%4\n\t"			\
+		   "sllx %4,32,%5\n\t"			\
+		   "srl %6,0,%3\n\t"			\
+		   "sub %1,%5,%5\n\t"			\
+		   "srlx %5,32,%5\n\t"			\
+		   "addcc %4,%5,%4\n\t"			\
+		   "srlx %7,32,%5\n\t"			\
+		   "mulx %3,%5,%3\n\t"			\
+		   "mulx %2,%5,%5\n\t"			\
+		   "sethi %%hi(0x80000000),%2\n\t"	\
+		   "addcc %4,%3,%4\n\t"			\
+		   "srlx %4,32,%4\n\t"			\
+		   "add %2,%2,%2\n\t"			\
+		   "movcc %%xcc,%%g0,%2\n\t"		\
+		   "addcc %5,%4,%5\n\t"			\
+		   "sllx %3,32,%3\n\t"			\
+		   "add %1,%3,%1\n\t"			\
+		   "add %5,%2,%0"			\
 	   : "=r" ((UDItype)(wh)),			\
 	     "=&r" ((UDItype)(wl)),			\
 	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \