Commit 5cb4ca07 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher

drm/amd/display: fix number of dcn21 dpm clock levels

These are specific to dcn21 and should not be increased for
reuse on other asics.
Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarChris Park <Chris.Park@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8c357309
...@@ -251,8 +251,8 @@ struct pp_smu_funcs_nv { ...@@ -251,8 +251,8 @@ struct pp_smu_funcs_nv {
#define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8 #define PP_SMU_NUM_SOCCLK_DPM_LEVELS 8
#define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8 #define PP_SMU_NUM_DCFCLK_DPM_LEVELS 8
#define PP_SMU_NUM_FCLK_DPM_LEVELS 8 #define PP_SMU_NUM_FCLK_DPM_LEVELS 4
#define PP_SMU_NUM_MEMCLK_DPM_LEVELS 8 #define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4
struct dpm_clock { struct dpm_clock {
uint32_t Freq; // In MHz uint32_t Freq; // In MHz
......
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