Commit 5d15798b authored by Shawn Guo's avatar Shawn Guo

Merge branch 'imx/soc' into imx/dt

parents cbd54fe0 c2053895
...@@ -75,6 +75,18 @@ i.MX6q generic board ...@@ -75,6 +75,18 @@ i.MX6q generic board
Required root node properties: Required root node properties:
- compatible = "fsl,imx6q"; - compatible = "fsl,imx6q";
Freescale Vybrid Platform Device Tree Bindings
----------------------------------------------
For the Vybrid SoC familiy all variants with DDR controller are supported,
which is the VF5xx and VF6xx series. Out of historical reasons, in most
places the kernel uses vf610 to refer to the whole familiy.
Required root node compatible property (one of them):
- compatible = "fsl,vf500";
- compatible = "fsl,vf510";
- compatible = "fsl,vf600";
- compatible = "fsl,vf610";
Freescale LS1021A Platform Device Tree Bindings Freescale LS1021A Platform Device Tree Bindings
------------------------------------------------ ------------------------------------------------
......
...@@ -32,8 +32,7 @@ ifeq ($(CONFIG_CPU_IDLE),y) ...@@ -32,8 +32,7 @@ ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
# i.MX6SX reuses i.MX6Q cpuidle driver obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o
obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6q.o
endif endif
ifdef CONFIG_SND_IMX_SOC ifdef CONFIG_SND_IMX_SOC
......
...@@ -96,15 +96,30 @@ static int clk_gate2_is_enabled(struct clk_hw *hw) ...@@ -96,15 +96,30 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
{ {
struct clk_gate2 *gate = to_clk_gate2(hw); struct clk_gate2 *gate = to_clk_gate2(hw);
if (gate->share_count) return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
return !!__clk_get_enable_count(hw->clk); }
else
return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); static void clk_gate2_disable_unused(struct clk_hw *hw)
{
struct clk_gate2 *gate = to_clk_gate2(hw);
unsigned long flags = 0;
u32 reg;
spin_lock_irqsave(gate->lock, flags);
if (!gate->share_count || *gate->share_count == 0) {
reg = readl(gate->reg);
reg &= ~(3 << gate->bit_idx);
writel(reg, gate->reg);
}
spin_unlock_irqrestore(gate->lock, flags);
} }
static struct clk_ops clk_gate2_ops = { static struct clk_ops clk_gate2_ops = {
.enable = clk_gate2_enable, .enable = clk_gate2_enable,
.disable = clk_gate2_disable, .disable = clk_gate2_disable,
.disable_unused = clk_gate2_disable_unused,
.is_enabled = clk_gate2_is_enabled, .is_enabled = clk_gate2_is_enabled,
}; };
......
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
* @base: base address of PLL registers * @base: base address of PLL registers
* @powerup_set: set POWER bit to power up the PLL * @powerup_set: set POWER bit to power up the PLL
* @div_mask: mask of divider bits * @div_mask: mask of divider bits
* @div_shift: shift of divider bits
* *
* IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
* is actually a multiplier, and always sits at bit 0. * is actually a multiplier, and always sits at bit 0.
...@@ -40,6 +41,7 @@ struct clk_pllv3 { ...@@ -40,6 +41,7 @@ struct clk_pllv3 {
void __iomem *base; void __iomem *base;
bool powerup_set; bool powerup_set;
u32 div_mask; u32 div_mask;
u32 div_shift;
}; };
#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
...@@ -97,7 +99,7 @@ static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, ...@@ -97,7 +99,7 @@ static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate) unsigned long parent_rate)
{ {
struct clk_pllv3 *pll = to_clk_pllv3(hw); struct clk_pllv3 *pll = to_clk_pllv3(hw);
u32 div = readl_relaxed(pll->base) & pll->div_mask; u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
return (div == 1) ? parent_rate * 22 : parent_rate * 20; return (div == 1) ? parent_rate * 22 : parent_rate * 20;
} }
...@@ -125,8 +127,8 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, ...@@ -125,8 +127,8 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
return -EINVAL; return -EINVAL;
val = readl_relaxed(pll->base); val = readl_relaxed(pll->base);
val &= ~pll->div_mask; val &= ~(pll->div_mask << pll->div_shift);
val |= div; val |= (div << pll->div_shift);
writel_relaxed(val, pll->base); writel_relaxed(val, pll->base);
return clk_pllv3_wait_lock(pll); return clk_pllv3_wait_lock(pll);
...@@ -295,6 +297,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, ...@@ -295,6 +297,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
case IMX_PLLV3_SYS: case IMX_PLLV3_SYS:
ops = &clk_pllv3_sys_ops; ops = &clk_pllv3_sys_ops;
break; break;
case IMX_PLLV3_USB_VF610:
pll->div_shift = 1;
case IMX_PLLV3_USB: case IMX_PLLV3_USB:
ops = &clk_pllv3_ops; ops = &clk_pllv3_ops;
pll->powerup_set = true; pll->powerup_set = true;
......
...@@ -172,11 +172,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) ...@@ -172,11 +172,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1); clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1);
clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1); clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1);
clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x1); clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x2);
clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f); clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f);
clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3); clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3);
clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f); clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f);
clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x1); clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x2);
clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
...@@ -267,6 +267,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) ...@@ -267,6 +267,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8)); clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9)); clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10)); clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
clk[VF610_CLK_UART4] = imx_clk_gate2("uart4", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(9));
clk[VF610_CLK_UART5] = imx_clk_gate2("uart5", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(10));
clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6)); clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7)); clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
...@@ -380,6 +382,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) ...@@ -380,6 +382,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1)); clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2)); clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));
imx_check_clocks(clk, ARRAY_SIZE(clk)); imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
......
...@@ -20,6 +20,7 @@ enum imx_pllv3_type { ...@@ -20,6 +20,7 @@ enum imx_pllv3_type {
IMX_PLLV3_GENERIC, IMX_PLLV3_GENERIC,
IMX_PLLV3_SYS, IMX_PLLV3_SYS,
IMX_PLLV3_USB, IMX_PLLV3_USB,
IMX_PLLV3_USB_VF610,
IMX_PLLV3_AV, IMX_PLLV3_AV,
IMX_PLLV3_ENET, IMX_PLLV3_ENET,
}; };
......
...@@ -70,6 +70,10 @@ void imx_set_soc_revision(unsigned int rev); ...@@ -70,6 +70,10 @@ void imx_set_soc_revision(unsigned int rev);
unsigned int imx_get_soc_revision(void); unsigned int imx_get_soc_revision(void);
void imx_init_revision_from_anatop(void); void imx_init_revision_from_anatop(void);
struct device *imx_soc_device_init(void); struct device *imx_soc_device_init(void);
void imx6_enable_rbc(bool enable);
void imx_gpc_set_arm_power_in_lpm(bool power_off);
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
enum mxc_cpu_pwr_mode { enum mxc_cpu_pwr_mode {
WAIT_CLOCKED, /* wfi only */ WAIT_CLOCKED, /* wfi only */
......
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/module.h>
#include <asm/cpuidle.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include "common.h"
#include "cpuidle.h"
static int imx6sx_idle_finish(unsigned long val)
{
cpu_do_idle();
return 0;
}
static int imx6sx_enter_wait(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
imx6q_set_lpm(WAIT_UNCLOCKED);
switch (index) {
case 1:
cpu_do_idle();
break;
case 2:
imx6_enable_rbc(true);
imx_gpc_set_arm_power_in_lpm(true);
imx_set_cpu_jump(0, v7_cpu_resume);
/* Need to notify there is a cpu pm operation. */
cpu_pm_enter();
cpu_cluster_pm_enter();
cpu_suspend(0, imx6sx_idle_finish);
cpu_cluster_pm_exit();
cpu_pm_exit();
imx_gpc_set_arm_power_in_lpm(false);
imx6_enable_rbc(false);
break;
default:
break;
}
imx6q_set_lpm(WAIT_CLOCKED);
return index;
}
static struct cpuidle_driver imx6sx_cpuidle_driver = {
.name = "imx6sx_cpuidle",
.owner = THIS_MODULE,
.states = {
/* WFI */
ARM_CPUIDLE_WFI_STATE,
/* WAIT */
{
.exit_latency = 50,
.target_residency = 75,
.flags = CPUIDLE_FLAG_TIMER_STOP,
.enter = imx6sx_enter_wait,
.name = "WAIT",
.desc = "Clock off",
},
/* WAIT + ARM power off */
{
/*
* ARM gating 31us * 5 + RBC clear 65us
* and some margin for SW execution, here set it
* to 300us.
*/
.exit_latency = 300,
.target_residency = 500,
.enter = imx6sx_enter_wait,
.name = "LOW-POWER-IDLE",
.desc = "ARM power off",
},
},
.state_count = 3,
.safe_state_index = 0,
};
int __init imx6sx_cpuidle_init(void)
{
imx6_enable_rbc(false);
/*
* set ARM power up/down timing to the fastest,
* sw2iso and sw can be set to one 32K cycle = 31us
* except for power up sw2iso which need to be
* larger than LDO ramp up time.
*/
imx_gpc_set_arm_power_up_timing(2, 1);
imx_gpc_set_arm_power_down_timing(1, 1);
return cpuidle_register(&imx6sx_cpuidle_driver, NULL);
}
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
extern int imx5_cpuidle_init(void); extern int imx5_cpuidle_init(void);
extern int imx6q_cpuidle_init(void); extern int imx6q_cpuidle_init(void);
extern int imx6sl_cpuidle_init(void); extern int imx6sl_cpuidle_init(void);
extern int imx6sx_cpuidle_init(void);
#else #else
static inline int imx5_cpuidle_init(void) static inline int imx5_cpuidle_init(void)
{ {
...@@ -27,4 +28,8 @@ static inline int imx6sl_cpuidle_init(void) ...@@ -27,4 +28,8 @@ static inline int imx6sl_cpuidle_init(void)
{ {
return 0; return 0;
} }
static inline int imx6sx_cpuidle_init(void)
{
return 0;
}
#endif #endif
...@@ -20,6 +20,10 @@ ...@@ -20,6 +20,10 @@
#define GPC_IMR1 0x008 #define GPC_IMR1 0x008
#define GPC_PGC_CPU_PDN 0x2a0 #define GPC_PGC_CPU_PDN 0x2a0
#define GPC_PGC_CPU_PUPSCR 0x2a4
#define GPC_PGC_CPU_PDNSCR 0x2a8
#define GPC_PGC_SW2ISO_SHIFT 0x8
#define GPC_PGC_SW_SHIFT 0x0
#define IMR_NUM 4 #define IMR_NUM 4
...@@ -27,6 +31,23 @@ static void __iomem *gpc_base; ...@@ -27,6 +31,23 @@ static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM]; static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM]; static u32 gpc_saved_imrs[IMR_NUM];
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
{
writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
}
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
{
writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
}
void imx_gpc_set_arm_power_in_lpm(bool power_off)
{
writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
}
void imx_gpc_pre_suspend(bool arm_power_off) void imx_gpc_pre_suspend(bool arm_power_off)
{ {
void __iomem *reg_imr1 = gpc_base + GPC_IMR1; void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
...@@ -34,7 +55,7 @@ void imx_gpc_pre_suspend(bool arm_power_off) ...@@ -34,7 +55,7 @@ void imx_gpc_pre_suspend(bool arm_power_off)
/* Tell GPC to power off ARM core when suspend */ /* Tell GPC to power off ARM core when suspend */
if (arm_power_off) if (arm_power_off)
writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN); imx_gpc_set_arm_power_in_lpm(arm_power_off);
for (i = 0; i < IMR_NUM; i++) { for (i = 0; i < IMR_NUM; i++) {
gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
...@@ -48,7 +69,7 @@ void imx_gpc_post_resume(void) ...@@ -48,7 +69,7 @@ void imx_gpc_post_resume(void)
int i; int i;
/* Keep ARM core powered on for other low-power modes */ /* Keep ARM core powered on for other low-power modes */
writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN); imx_gpc_set_arm_power_in_lpm(false);
for (i = 0; i < IMR_NUM; i++) for (i = 0; i < IMR_NUM; i++)
writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
......
...@@ -90,7 +90,7 @@ static void __init imx6sx_init_irq(void) ...@@ -90,7 +90,7 @@ static void __init imx6sx_init_irq(void)
static void __init imx6sx_init_late(void) static void __init imx6sx_init_late(void)
{ {
imx6q_cpuidle_init(); imx6sx_cpuidle_init();
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
......
...@@ -13,11 +13,14 @@ ...@@ -13,11 +13,14 @@
#include <asm/hardware/cache-l2x0.h> #include <asm/hardware/cache-l2x0.h>
static const char * const vf610_dt_compat[] __initconst = { static const char * const vf610_dt_compat[] __initconst = {
"fsl,vf500",
"fsl,vf510",
"fsl,vf600",
"fsl,vf610", "fsl,vf610",
NULL, NULL,
}; };
DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)") DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF5xx/VF6xx (Device Tree)")
.l2c_aux_val = 0, .l2c_aux_val = 0,
.l2c_aux_mask = ~0, .l2c_aux_mask = ~0,
.dt_compat = vf610_dt_compat, .dt_compat = vf610_dt_compat,
......
...@@ -205,7 +205,7 @@ void imx6q_set_int_mem_clk_lpm(bool enable) ...@@ -205,7 +205,7 @@ void imx6q_set_int_mem_clk_lpm(bool enable)
writel_relaxed(val, ccm_base + CGPR); writel_relaxed(val, ccm_base + CGPR);
} }
static void imx6q_enable_rbc(bool enable) void imx6_enable_rbc(bool enable)
{ {
u32 val; u32 val;
...@@ -359,17 +359,16 @@ static int imx6q_pm_enter(suspend_state_t state) ...@@ -359,17 +359,16 @@ static int imx6q_pm_enter(suspend_state_t state)
* RBC setting, so we do NOT need to do that here. * RBC setting, so we do NOT need to do that here.
*/ */
if (!imx6_suspend_in_ocram_fn) if (!imx6_suspend_in_ocram_fn)
imx6q_enable_rbc(true); imx6_enable_rbc(true);
imx_gpc_pre_suspend(true); imx_gpc_pre_suspend(true);
imx_anatop_pre_suspend(); imx_anatop_pre_suspend();
imx_set_cpu_jump(0, v7_cpu_resume);
/* Zzz ... */ /* Zzz ... */
cpu_suspend(0, imx6q_suspend_finish); cpu_suspend(0, imx6q_suspend_finish);
if (cpu_is_imx6q() || cpu_is_imx6dl()) if (cpu_is_imx6q() || cpu_is_imx6dl())
imx_smp_prepare(); imx_smp_prepare();
imx_anatop_post_resume(); imx_anatop_post_resume();
imx_gpc_post_resume(); imx_gpc_post_resume();
imx6q_enable_rbc(false); imx6_enable_rbc(false);
imx6q_enable_wb(false); imx6q_enable_wb(false);
imx6q_set_int_mem_clk_lpm(true); imx6q_set_int_mem_clk_lpm(true);
imx6q_set_lpm(WAIT_CLOCKED); imx6q_set_lpm(WAIT_CLOCKED);
......
...@@ -192,6 +192,7 @@ ...@@ -192,6 +192,7 @@
#define VF610_PLL5_BYPASS 179 #define VF610_PLL5_BYPASS 179
#define VF610_PLL6_BYPASS 180 #define VF610_PLL6_BYPASS 180
#define VF610_PLL7_BYPASS 181 #define VF610_PLL7_BYPASS 181
#define VF610_CLK_END 182 #define VF610_CLK_SNVS 182
#define VF610_CLK_END 183
#endif /* __DT_BINDINGS_CLOCK_VF610_H */ #endif /* __DT_BINDINGS_CLOCK_VF610_H */
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