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Commit 5d904e3c authored by Tvrtko Ursulin's avatar Tvrtko Ursulin Committed by Chris Wilson
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drm/i915: Pass in intel_gt at some for_each_engine sites 

Where the function, or code segment, operates on intel_gt, we need to
start passing it instead of i915 to for_each_engine(_masked).

This is another partial step in migration of i915->engines[] to
gt->engines[].
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191017094500.21831-2-tvrtko.ursulin@linux.intel.com
parent a50134b1
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Showing with 67 additions and 67 deletions
drivers/gpu/drm/i915/gt/intel_engine_cs.c
View file @ 5d904e3c
......@@ -1123,7 +1123,7 @@ bool intel_engines_are_idle(struct intel_gt *gt)
if (!READ_ONCE(gt->awake))
return true;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
if (!intel_engine_is_idle(engine))
return false;
}
......@@ -1136,7 +1136,7 @@ void intel_engines_reset_default_submission(struct intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
engine->set_default_submission(engine);
}
......
drivers/gpu/drm/i915/gt/intel_gt.c
View file @ 5d904e3c
......@@ -197,7 +197,7 @@ static void gen6_check_faults(struct intel_gt *gt)
enum intel_engine_id id;
u32 fault;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
DRM_DEBUG_DRIVER("Unexpected fault\n"
......
drivers/gpu/drm/i915/gt/intel_gt_pm.c
View file @ 5d904e3c
......@@ -136,16 +136,16 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
intel_uc_sanitize(&gt->uc);
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
if (engine->reset.prepare)
engine->reset.prepare(engine);
if (reset_engines(gt) || force) {
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
__intel_engine_reset(engine, false);
}
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
if (engine->reset.finish)
engine->reset.finish(engine);
}
......@@ -177,7 +177,7 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
intel_rc6_sanitize(&gt->rc6);
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct intel_context *ce;
intel_engine_pm_get(engine);
......
drivers/gpu/drm/i915/gt/intel_gt_requests.c
View file @ 5d904e3c
......@@ -25,7 +25,7 @@ static void flush_submission(struct intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
intel_engine_flush_submission(engine);
}
......
drivers/gpu/drm/i915/gt/intel_hangcheck.c
View file @ 5d904e3c
......@@ -281,7 +281,7 @@ static void hangcheck_elapsed(struct work_struct *work)
*/
intel_uncore_arm_unclaimed_mmio_detection(gt->uncore);
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct hangcheck hc;
intel_engine_breadcrumbs_irq(engine);
......@@ -303,7 +303,7 @@ static void hangcheck_elapsed(struct work_struct *work)
if (GEM_SHOW_DEBUG() && (hung | stuck)) {
struct drm_printer p = drm_debug_printer("hangcheck");
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
if (intel_engine_is_idle(engine))
continue;
......
drivers/gpu/drm/i915/gt/intel_reset.c
View file @ 5d904e3c
......@@ -682,7 +682,7 @@ static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
intel_engine_mask_t awake = 0;
enum intel_engine_id id;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
if (intel_engine_pm_get_if_awake(engine))
awake |= engine->mask;
reset_prepare_engine(engine);
......@@ -712,7 +712,7 @@ static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
if (err)
return err;
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
__intel_engine_reset(engine, stalled_mask & engine->mask);
i915_gem_restore_fences(gt->ggtt);
......@@ -733,7 +733,7 @@ static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
struct intel_engine_cs *engine;
enum intel_engine_id id;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
reset_finish_engine(engine);
if (awake & engine->mask)
intel_engine_pm_put(engine);
......@@ -769,7 +769,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
struct drm_printer p = drm_debug_printer(__func__);
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
intel_engine_dump(engine, &p, "%s\n", engine->name);
}
......@@ -786,7 +786,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
__intel_gt_reset(gt, ALL_ENGINES);
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
engine->submit_request = nop_submit_request;
/*
......@@ -798,7 +798,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt)
set_bit(I915_WEDGED, &gt->reset.flags);
/* Mark all executing requests as skipped */
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
engine->cancel_requests(engine);
reset_finish(gt, awake);
......@@ -934,7 +934,7 @@ static int resume(struct intel_gt *gt)
enum intel_engine_id id;
int ret;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
ret = engine->resume(engine);
if (ret)
return ret;
......@@ -1234,7 +1234,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
synchronize_rcu_expedited();
/* Prevent any other reset-engine attempt. */
for_each_engine(engine, gt->i915, tmp) {
for_each_engine(engine, gt, tmp) {
while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
&gt->reset.flags))
wait_on_bit(&gt->reset.flags,
......@@ -1244,7 +1244,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
intel_gt_reset_global(gt, engine_mask, msg);
for_each_engine(engine, gt->i915, tmp)
for_each_engine(engine, gt, tmp)
clear_bit_unlock(I915_RESET_ENGINE + engine->id,
&gt->reset.flags);
clear_bit_unlock(I915_RESET_BACKOFF, &gt->reset.flags);
......
drivers/gpu/drm/i915/gt/selftest_context.c
View file @ 5d904e3c
......@@ -159,7 +159,7 @@ static int live_context_size(void *arg)
if (IS_ERR(fixme))
return PTR_ERR(fixme);
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct {
struct drm_i915_gem_object *state;
void *pinned;
......@@ -305,7 +305,7 @@ static int live_active_context(void *arg)
goto out_file;
}
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
err = __live_active_context(engine, fixme);
if (err)
break;
......@@ -415,7 +415,7 @@ static int live_remote_context(void *arg)
goto out_file;
}
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
err = __live_remote_context(engine, fixme);
if (err)
break;
......
drivers/gpu/drm/i915/gt/selftest_engine_pm.c
View file @ 5d904e3c
......@@ -25,7 +25,7 @@ static int live_engine_pm(void *arg)
}
GEM_BUG_ON(intel_gt_pm_is_awake(gt));
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
const typeof(*igt_atomic_phases) *p;
for (p = igt_atomic_phases; p->name; p++) {
......
drivers/gpu/drm/i915/gt/selftest_hangcheck.c
View file @ 5d904e3c
......@@ -323,7 +323,7 @@ static int igt_hang_sanitycheck(void *arg)
if (err)
return err;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct intel_wedge_me w;
long timeout;
......@@ -400,7 +400,7 @@ static int igt_reset_nop(void *arg)
reset_count = i915_reset_count(global);
count = 0;
do {
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
int i;
for (i = 0; i < 16; i++) {
......@@ -471,7 +471,7 @@ static int igt_reset_nop_engine(void *arg)
}
i915_gem_context_clear_bannable(ctx);
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
unsigned int reset_count, reset_engine_count;
unsigned int count;
IGT_TIMEOUT(end_time);
......@@ -560,7 +560,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active)
return err;
}
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
unsigned int reset_count, reset_engine_count;
IGT_TIMEOUT(end_time);
......@@ -782,7 +782,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
h.ctx->sched.priority = 1024;
}
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct active_engine threads[I915_NUM_ENGINES] = {};
unsigned long device = i915_reset_count(global);
unsigned long count = 0, reported;
......@@ -800,7 +800,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
}
memset(threads, 0, sizeof(threads));
for_each_engine(other, gt->i915, tmp) {
for_each_engine(other, gt, tmp) {
struct task_struct *tsk;
threads[tmp].resets =
......@@ -914,7 +914,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
}
unwind:
for_each_engine(other, gt->i915, tmp) {
for_each_engine(other, gt, tmp) {
int ret;
if (!threads[tmp].task)
......@@ -1335,7 +1335,7 @@ static int wait_for_others(struct intel_gt *gt,
struct intel_engine_cs *engine;
enum intel_engine_id id;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
if (engine == exclude)
continue;
......@@ -1363,7 +1363,7 @@ static int igt_reset_queue(void *arg)
if (err)
goto unlock;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct i915_request *prev;
IGT_TIMEOUT(end_time);
unsigned int count;
......@@ -1651,7 +1651,7 @@ static int igt_reset_engines_atomic(void *arg)
struct intel_engine_cs *engine;
enum intel_engine_id id;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
err = igt_atomic_reset_engine(engine, p);
if (err)
goto out;
......
drivers/gpu/drm/i915/gt/selftest_lrc.c
View file @ 5d904e3c
......@@ -123,7 +123,7 @@ static int live_unlite_restore(struct intel_gt *gt, int prio)
goto err_spin;
err = 0;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct intel_context *ce[2] = {};
struct i915_request *rq[2];
struct igt_live_test t;
......@@ -384,7 +384,7 @@ slice_semaphore_queue(struct intel_engine_cs *outer,
return PTR_ERR(head);
i915_request_get(head);
for_each_engine(engine, outer->i915, id) {
for_each_engine(engine, outer->gt, id) {
for (i = 0; i < count; i++) {
struct i915_request *rq;
......@@ -456,7 +456,7 @@ static int live_timeslice_preempt(void *arg)
struct intel_engine_cs *engine;
enum intel_engine_id id;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
if (!intel_engine_has_preemption(engine))
continue;
......@@ -532,7 +532,7 @@ static int live_busywait_preempt(void *arg)
if (err)
goto err_map;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct i915_request *lo, *hi;
struct igt_live_test t;
u32 *cs;
......@@ -708,7 +708,7 @@ static int live_preempt(void *arg)
ctx_lo->sched.priority =
I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct igt_live_test t;
struct i915_request *rq;
......@@ -804,7 +804,7 @@ static int live_late_preempt(void *arg)
/* Make sure ctx_lo stays before ctx_hi until we trigger preemption. */
ctx_lo->sched.priority = I915_USER_PRIORITY(1);
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct igt_live_test t;
struct i915_request *rq;
......@@ -929,7 +929,7 @@ static int live_nopreempt(void *arg)
goto err_client_a;
b.ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX);
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct i915_request *rq_a, *rq_b;
if (!intel_engine_has_preemption(engine))
......@@ -1040,7 +1040,7 @@ static int live_suppress_self_preempt(void *arg)
if (preempt_client_init(gt, &b))
goto err_client_a;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct i915_request *rq_a, *rq_b;
int depth;
......@@ -1207,7 +1207,7 @@ static int live_suppress_wait_preempt(void *arg)
if (preempt_client_init(gt, &client[3])) /* bystander */
goto err_client_2;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
int depth;
if (!intel_engine_has_preemption(engine))
......@@ -1318,7 +1318,7 @@ static int live_chain_preempt(void *arg)
if (preempt_client_init(gt, &lo))
goto err_client_hi;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct i915_sched_attr attr = {
.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX),
};
......@@ -1467,7 +1467,7 @@ static int live_preempt_hang(void *arg)
ctx_lo->sched.priority =
I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct i915_request *rq;
if (!intel_engine_has_preemption(engine))
......@@ -1656,7 +1656,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
unsigned long count;
int err = 0;
for_each_engine(engine, smoke->gt->i915, id) {
for_each_engine(engine, smoke->gt, id) {
arg[id] = *smoke;
arg[id].engine = engine;
if (!(flags & BATCH))
......@@ -1673,7 +1673,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags)
}
count = 0;
for_each_engine(engine, smoke->gt->i915, id) {
for_each_engine(engine, smoke->gt, id) {
int status;
if (IS_ERR_OR_NULL(tsk[id]))
......@@ -1702,7 +1702,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags)
count = 0;
do {
for_each_engine(smoke->engine, smoke->gt->i915, id) {
for_each_engine(smoke->engine, smoke->gt, id) {
struct i915_gem_context *ctx = smoke_context(smoke);
int err;
......@@ -1937,7 +1937,7 @@ static int live_virtual_engine(void *arg)
if (USES_GUC_SUBMISSION(gt->i915))
return 0;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
err = nop_virtual_engine(gt, &engine, 1, 1, 0);
if (err) {
pr_err("Failed to wrap engine %s: err=%d\n",
......@@ -2270,7 +2270,7 @@ static int bond_virtual_engine(struct intel_gt *gt,
err = 0;
rq[0] = ERR_PTR(-ENOMEM);
for_each_engine(master, gt->i915, id) {
for_each_engine(master, gt, id) {
struct i915_sw_fence fence = {};
if (master->class == class)
......@@ -2508,7 +2508,7 @@ static int live_lrc_layout(void *arg)
return -ENOMEM;
err = 0;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
u32 *hw, *lrc;
int dw;
......@@ -2701,7 +2701,7 @@ static int live_lrc_state(void *arg)
goto out_close;
}
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
err = __live_lrc_state(fixme, engine, scratch);
if (err)
break;
......@@ -2844,7 +2844,7 @@ static int live_gpr_clear(void *arg)
goto out_close;
}
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
err = __live_gpr_clear(fixme, engine, scratch);
if (err)
break;
......
drivers/gpu/drm/i915/gt/selftest_reset.c
View file @ 5d904e3c
......@@ -125,7 +125,7 @@ static int igt_atomic_engine_reset(void *arg)
if (!igt_force_reset(gt))
goto out_unlock;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
tasklet_disable_nosync(&engine->execlists.tasklet);
intel_engine_pm_get(engine);
......
drivers/gpu/drm/i915/gt/selftest_timeline.c
View file @ 5d904e3c
......@@ -519,7 +519,7 @@ static int live_hwsp_engine(void *arg)
return -ENOMEM;
count = 0;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
if (!intel_engine_can_store_dword(engine))
continue;
......@@ -594,7 +594,7 @@ static int live_hwsp_alternate(void *arg)
count = 0;
for (n = 0; n < NUM_TIMELINES; n++) {
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct intel_timeline *tl;
struct i915_request *rq;
......@@ -666,7 +666,7 @@ static int live_hwsp_wrap(void *arg)
if (err)
goto out_free;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
const u32 *hwsp_seqno[2];
struct i915_request *rq;
u32 seqno[2];
......@@ -766,7 +766,7 @@ static int live_hwsp_recycle(void *arg)
*/
count = 0;
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
IGT_TIMEOUT(end_time);
if (!intel_engine_can_store_dword(engine))
......
drivers/gpu/drm/i915/gt/selftest_workarounds.c
View file @ 5d904e3c
......@@ -69,7 +69,7 @@ reference_lists_init(struct intel_gt *gt, struct wa_lists *lists)
gt_init_workarounds(gt->i915, &lists->gt_wa_list);
wa_init_finish(&lists->gt_wa_list);
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
struct i915_wa_list *wal = &lists->engine[id].wa_list;
wa_init_start(wal, "REF", engine->name);
......@@ -88,7 +88,7 @@ reference_lists_fini(struct intel_gt *gt, struct wa_lists *lists)
struct intel_engine_cs *engine;
enum intel_engine_id id;
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
intel_wa_list_free(&lists->engine[id].wa_list);
intel_wa_list_free(&lists->gt_wa_list);
......@@ -726,7 +726,7 @@ static int live_dirty_whitelist(void *arg)
goto out_file;
}
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
if (engine->whitelist.count == 0)
continue;
......@@ -750,7 +750,7 @@ static int live_reset_whitelist(void *arg)
/* If we reset the gpu, we should not lose the RING_NONPRIV */
igt_global_reset_lock(gt);
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
if (engine->whitelist.count == 0)
continue;
......@@ -1048,7 +1048,7 @@ static int live_isolated_whitelist(void *arg)
i915_vm_put(vm);
}
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
if (!engine->kernel_context->vm)
continue;
......
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
View file @ 5d904e3c
......@@ -1020,7 +1020,7 @@ static void guc_interrupts_capture(struct intel_gt *gt)
* to GuC
*/
irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
/* route USER_INTERRUPT to Host, all others are sent to GuC. */
......@@ -1068,7 +1068,7 @@ static void guc_interrupts_release(struct intel_gt *gt)
*/
irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
/* route all GT interrupts to the host */
......@@ -1151,7 +1151,7 @@ int intel_guc_submission_enable(struct intel_guc *guc)
/* Take over from manual control of ELSP (execlists) */
guc_interrupts_capture(gt);
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
engine->set_default_submission = guc_set_default_submission;
engine->set_default_submission(engine);
}
......
drivers/gpu/drm/i915/selftests/igt_reset.c
View file @ 5d904e3c
......@@ -22,7 +22,7 @@ void igt_global_reset_lock(struct intel_gt *gt)
wait_event(gt->reset.queue,
!test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
for_each_engine(engine, gt->i915, id) {
for_each_engine(engine, gt, id) {
while (test_and_set_bit(I915_RESET_ENGINE + id,
&gt->reset.flags))
wait_on_bit(&gt->reset.flags, I915_RESET_ENGINE + id,
......@@ -35,7 +35,7 @@ void igt_global_reset_unlock(struct intel_gt *gt)
struct intel_engine_cs *engine;
enum intel_engine_id id;
for_each_engine(engine, gt->i915, id)
for_each_engine(engine, gt, id)
clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
clear_bit(I915_RESET_BACKOFF, &gt->reset.flags);
......
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