Commit 5e540a5a authored by Shawn Guo's avatar Shawn Guo

ARM: imx6: add missing twd_clk for imx6q clock

With commit 5def51b0 (ARM: 7211/1: smp_twd: get the rate from a clock)
hitting mainline, if we do not have a twd_clk for lookup, we will see
the following error message in boot log.

 smp_twd: clock not found: -2

Actually we should add this clock regardless of the error message,
so that we can:

 * Avoid the local timer calibrating at boot time
 * Make the local timer cpufreq aware on imx6q
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent dcd6c922
...@@ -814,6 +814,16 @@ DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg); ...@@ -814,6 +814,16 @@ DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg);
DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg); DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg);
DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg); DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg);
static unsigned long twd_clk_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / 2;
}
static struct clk twd_clk = {
.parent = &arm_clk,
.get_rate = twd_clk_get_rate,
};
static unsigned long pll2_200m_get_rate(struct clk *clk) static unsigned long pll2_200m_get_rate(struct clk *clk)
{ {
return clk_get_rate(clk->parent) / 2; return clk_get_rate(clk->parent) / 2;
...@@ -1894,6 +1904,7 @@ static struct clk_lookup lookups[] = { ...@@ -1894,6 +1904,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk), _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk),
_REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk), _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk),
_REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk), _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk),
_REGISTER_CLOCK("smp_twd", NULL, twd_clk),
_REGISTER_CLOCK(NULL, "ckih", ckih_clk), _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
_REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk), _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk),
_REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk), _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk),
......
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