Commit 5ec5e792 authored by Olof Johansson's avatar Olof Johansson

Merge tag 'davinci-for-v4.1/mcasp' of...

Merge tag 'davinci-for-v4.1/mcasp' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/cleanup

Merge "DaVinci McASP changes for v4.1" from Sekhar Nori:

This pull request contains cleanups and non-urgent fixes for DaVinci
McASP platform support code.

* tag 'davinci-for-v4.1/mcasp' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: davinci: dm646x: Add interrupt resource for McASPs
  ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x
  ARM: davinci: dm646x: Clean up the McASP DMA resources
  ARM: davinci: devices-da8xx: Add support for McASP2 on da830
  ARM: davinci: devices-da8xx: Clean up and correct the McASP device creation
  ARM: davinci: devices-da8xx: Add interrupt resource to McASP structs
  ARM: davinci: devices-da8xx: Add resource name for the McASP DMA request
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 9fb71bc0 6cfdf55b
......@@ -21,6 +21,9 @@
/* Bases of da830 McASP1 register banks */
#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
/* Bases of da830 McASP2 register banks */
#define DAVINCI_DA830_MCASP2_REG_BASE 0x01D08000
/* EDMA channels of dm644x and dm355 */
#define DAVINCI_DMA_ASP0_TX 2
#define DAVINCI_DMA_ASP0_RX 3
......@@ -40,6 +43,10 @@
#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
/* EDMA channels of da830 McASP2 */
#define DAVINCI_DA830_DMA_MCASP2_AREVT 4
#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5
/* Interrupts */
#define DAVINCI_ASP0_RX_INT IRQ_MBRINT
#define DAVINCI_ASP0_TX_INT IRQ_MBXINT
......
......@@ -463,16 +463,23 @@ static struct resource da830_mcasp1_resources[] = {
},
/* TX event */
{
.name = "tx",
.start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
.end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
.flags = IORESOURCE_DMA,
},
/* RX event */
{
.name = "rx",
.start = DAVINCI_DA830_DMA_MCASP1_AREVT,
.end = DAVINCI_DA830_DMA_MCASP1_AREVT,
.flags = IORESOURCE_DMA,
},
{
.name = "common",
.start = IRQ_DA8XX_MCASPINT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device da830_mcasp1_device = {
......@@ -482,6 +489,41 @@ static struct platform_device da830_mcasp1_device = {
.resource = da830_mcasp1_resources,
};
static struct resource da830_mcasp2_resources[] = {
{
.name = "mpu",
.start = DAVINCI_DA830_MCASP2_REG_BASE,
.end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
.flags = IORESOURCE_MEM,
},
/* TX event */
{
.name = "tx",
.start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
.end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
.flags = IORESOURCE_DMA,
},
/* RX event */
{
.name = "rx",
.start = DAVINCI_DA830_DMA_MCASP2_AREVT,
.end = DAVINCI_DA830_DMA_MCASP2_AREVT,
.flags = IORESOURCE_DMA,
},
{
.name = "common",
.start = IRQ_DA8XX_MCASPINT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device da830_mcasp2_device = {
.name = "davinci-mcasp",
.id = 2,
.num_resources = ARRAY_SIZE(da830_mcasp2_resources),
.resource = da830_mcasp2_resources,
};
static struct resource da850_mcasp_resources[] = {
{
.name = "mpu",
......@@ -491,16 +533,23 @@ static struct resource da850_mcasp_resources[] = {
},
/* TX event */
{
.name = "tx",
.start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
.end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
.flags = IORESOURCE_DMA,
},
/* RX event */
{
.name = "rx",
.start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
.end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
.flags = IORESOURCE_DMA,
},
{
.name = "common",
.start = IRQ_DA8XX_MCASPINT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device da850_mcasp_device = {
......@@ -512,14 +561,31 @@ static struct platform_device da850_mcasp_device = {
void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
{
/* DA830/OMAP-L137 has 3 instances of McASP */
if (cpu_is_davinci_da830() && id == 1) {
da830_mcasp1_device.dev.platform_data = pdata;
platform_device_register(&da830_mcasp1_device);
} else if (cpu_is_davinci_da850()) {
da850_mcasp_device.dev.platform_data = pdata;
platform_device_register(&da850_mcasp_device);
struct platform_device *pdev;
switch (id) {
case 0:
/* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
pdev = &da850_mcasp_device;
break;
case 1:
/* Valid for DA830/OMAP-L137 only */
if (!cpu_is_davinci_da830())
return;
pdev = &da830_mcasp1_device;
break;
case 2:
/* Valid for DA830/OMAP-L137 only */
if (!cpu_is_davinci_da830())
return;
pdev = &da830_mcasp2_device;
break;
default:
return;
}
pdev->dev.platform_data = pdata;
platform_device_register(pdev);
}
static struct resource da8xx_pruss_resources[] = {
......
......@@ -493,7 +493,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
[IRQ_DM646X_EMACMISCINT] = 7,
[IRQ_DM646X_MCASP0TXINT] = 7,
[IRQ_DM646X_MCASP0RXINT] = 7,
[IRQ_AEMIFINT] = 7,
[IRQ_DM646X_RESERVED_3] = 7,
[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
[IRQ_TINT0_TINT34] = 7, /* clocksource */
......@@ -610,19 +609,31 @@ static struct resource dm646x_mcasp0_resources[] = {
.end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
.flags = IORESOURCE_MEM,
},
/* first TX, then RX */
{
.name = "tx",
.start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
.end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
.flags = IORESOURCE_DMA,
},
{
.name = "rx",
.start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
.end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
.flags = IORESOURCE_DMA,
},
{
.name = "tx",
.start = IRQ_DM646X_MCASP0TXINT,
.flags = IORESOURCE_IRQ,
},
{
.name = "rx",
.start = IRQ_DM646X_MCASP0RXINT,
.flags = IORESOURCE_IRQ,
},
};
/* DIT mode only, rx is not supported */
static struct resource dm646x_mcasp1_resources[] = {
{
.name = "mpu",
......@@ -630,17 +641,16 @@ static struct resource dm646x_mcasp1_resources[] = {
.end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
.flags = IORESOURCE_MEM,
},
/* DIT mode, only TX event */
{
.name = "tx",
.start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
.end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
.flags = IORESOURCE_DMA,
},
/* DIT mode, dummy entry */
{
.start = -1,
.end = -1,
.flags = IORESOURCE_DMA,
.name = "tx",
.start = IRQ_DM646X_MCASP1TXINT,
.flags = IORESOURCE_IRQ,
},
};
......
......@@ -129,8 +129,8 @@
#define IRQ_DM646X_EMACMISCINT 27
#define IRQ_DM646X_MCASP0TXINT 28
#define IRQ_DM646X_MCASP0RXINT 29
#define IRQ_DM646X_MCASP1TXINT 30
#define IRQ_DM646X_RESERVED_3 31
#define IRQ_DM646X_MCASP1TXINT 32
#define IRQ_DM646X_VLQINT 38
#define IRQ_DM646X_UARTINT2 42
#define IRQ_DM646X_SPINT0 43
......
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