drm/nv40/fb: start bashing zcomp registers on relevant chipsets

Always bashing "disabled" for now, actual compressing coming up...
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/core/include/subdev/fb.h

@@ -145,9 +145,11 @@ void nv30_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
 void nv30_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);
 
 int  nv41_fb_init(struct nouveau_object *);
-int  nv44_fb_init(struct nouveau_object *);
 void nv41_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
 
+int  nv44_fb_init(struct nouveau_object *);
+void nv44_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
+
 void nv46_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
 		       u32 pitch, u32 flags, struct nouveau_fb_tile *);
 

drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c

@@ -30,6 +30,13 @@ struct nv40_fb_priv {
 	struct nouveau_fb base;
 };
 
+static void
+nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
+		  struct nouveau_fb_tile *tile)
+{
+	tile->zcomp = 0x00000000;
+}
+
 static int
 nv40_fb_init(struct nouveau_object *object)
 {
@@ -72,8 +79,9 @@ nv40_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	priv->base.memtype_valid = nv04_fb_memtype_valid;
 	priv->base.tile.regions = 8;
 	priv->base.tile.init = nv30_fb_tile_init;
+	priv->base.tile.comp = nv40_fb_tile_comp;
 	priv->base.tile.fini = nv30_fb_tile_fini;
-	priv->base.tile.prog = nv10_fb_tile_prog;
+	priv->base.tile.prog = nv20_fb_tile_prog;
 	return nouveau_fb_created(&priv->base);
 }
 

drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c

@@ -36,9 +36,9 @@ nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
 	nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
 	nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
 	nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
+	nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp);
 }
 
-
 int
 nv41_fb_init(struct nouveau_object *object)
 {

drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c

@@ -40,6 +40,14 @@ nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
 	tile->pitch = pitch;
 }
 
+void
+nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
+{
+	nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
+	nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch);
+	nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr);
+}
+
 int
 nv44_fb_init(struct nouveau_object *object)
 {
@@ -84,7 +92,7 @@ nv44_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	priv->base.tile.regions = 12;
 	priv->base.tile.init = nv44_fb_tile_init;
 	priv->base.tile.fini = nv30_fb_tile_fini;
-	priv->base.tile.prog = nv41_fb_tile_prog;
+	priv->base.tile.prog = nv44_fb_tile_prog;
 	return nouveau_fb_created(&priv->base);
 }
 

drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c

@@ -73,7 +73,7 @@ nv46_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	priv->base.tile.regions = 15;
 	priv->base.tile.init = nv46_fb_tile_init;
 	priv->base.tile.fini = nv30_fb_tile_fini;
-	priv->base.tile.prog = nv41_fb_tile_prog;
+	priv->base.tile.prog = nv44_fb_tile_prog;
 	return nouveau_fb_created(&priv->base);
 }
 

drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c

@@ -50,7 +50,7 @@ nv4e_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	priv->base.tile.regions = 12;
 	priv->base.tile.init = nv46_fb_tile_init;
 	priv->base.tile.fini = nv30_fb_tile_fini;
-	priv->base.tile.prog = nv41_fb_tile_prog;
+	priv->base.tile.prog = nv44_fb_tile_prog;
 	return nouveau_fb_created(&priv->base);
 }