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Commit 60083ee0 authored by Bartlomiej Zolnierkiewicz's avatar Bartlomiej Zolnierkiewicz Committed by Greg Kroah-Hartman
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Staging: rtl8192su: remove RTL8192SE ifdefs 

Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent bd7b22c9
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Showing with 12 additions and 588 deletions
drivers/staging/rtl8192su/ieee80211/ieee80211_softmac_wx.c
View file @ 60083ee0
......@@ -327,9 +327,7 @@ void ieee80211_wx_sync_scan_wq(struct work_struct *work)
ieee->state = IEEE80211_LINKED_SCANNING;
ieee->link_change(ieee->dev);
#ifndef RTL8192SE
ieee->InitialGainHandler(ieee->dev,IG_Backup);
#endif
if (ieee->SetFwCmdHandler)
{
ieee->SetFwCmdHandler(ieee->dev, FW_CMD_DIG_HALT);
......@@ -356,9 +354,7 @@ void ieee80211_wx_sync_scan_wq(struct work_struct *work)
ieee->set_chan(ieee->dev, chan);
}
#ifndef RTL8192SE
ieee->InitialGainHandler(ieee->dev,IG_Restore);
#endif
if (ieee->SetFwCmdHandler)
{
ieee->SetFwCmdHandler(ieee->dev, FW_CMD_DIG_RESUME);
......
drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c
View file @ 60083ee0
......@@ -495,7 +495,7 @@ void ieee80211_query_protectionmode(struct ieee80211_device* ieee, cb_desc* tcb_
{
tcb_desc->bCTSEnable = true;
tcb_desc->rts_rate = MGN_24M;
#if defined(RTL8192SE) || defined(RTL8192SU)
#if defined(RTL8192SU)
tcb_desc->bRTSEnable = false;
#else
tcb_desc->bRTSEnable = true;
......
drivers/staging/rtl8192su/ieee80211/rtl819x_HTProc.c
View file @ 60083ee0
......@@ -516,7 +516,7 @@ bool HTIOTActIsDisableMCSTwoSpatialStream(struct ieee80211_device* ieee)
//#endif
#endif
#if 1
#if (defined(RTL8192SE) || (defined(RTL8192SU)))
#if defined(RTL8192SU)
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
if(ieee->is_ap_in_wep_tkip && ieee->is_ap_in_wep_tkip(ieee->dev))
{
......@@ -595,7 +595,7 @@ u8 HTIOTActIsForcedRTSCTS(struct ieee80211_device *ieee, struct ieee80211_networ
u8 retValue = 0;
printk("============>%s(), %d\n", __FUNCTION__, network->realtek_cap_exit);
// Force protection
#if defined(RTL8192SE) || defined(RTL8192SU)
#if defined(RTL8192SU)
if(ieee->pHTInfo->bCurrentHTSupport)
{
//if(!network->realtek_cap_exit)
......@@ -621,14 +621,12 @@ HTIOTActIsForcedAMSDU8K(struct ieee80211_device *ieee, struct ieee80211_network
u8 HTIOTActIsCCDFsync(u8* PeerMacAddr)
{
u8 retValue = 0;
#ifndef RTL8192SE
if( (memcmp(PeerMacAddr, UNKNOWN_BORADCOM, 3)==0) ||
(memcmp(PeerMacAddr, LINKSYSWRT330_LINKSYSWRT300_BROADCOM, 3)==0) ||
(memcmp(PeerMacAddr, LINKSYSWRT350_LINKSYSWRT150_BROADCOM, 3) ==0))
{
retValue = 1;
}
#endif
return retValue;
}
......@@ -642,7 +640,7 @@ HTIOCActRejcectADDBARequest(struct ieee80211_network *network)
//if(IS_HARDWARE_TYPE_8192SE(Adapter) ||
// IS_HARDWARE_TYPE_8192SU(Adapter)
//)
#if (defined RTL8192SE || defined RTL8192SU)
#if defined RTL8192SU
{
// Do not reject ADDBA REQ because some of the AP may
// keep on sending ADDBA REQ qhich cause DHCP fail or ping loss!
......@@ -735,7 +733,7 @@ HTIOTActIsDisableTx40MHz(struct ieee80211_device* ieee,struct ieee80211_network
{
u8 retValue = 0;
#if (defined RTL8192SU || defined RTL8192SE)
#if defined RTL8192SU
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
if( (KEY_TYPE_WEP104 == ieee->pairwise_key_type) ||
(KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
......@@ -756,7 +754,7 @@ HTIOTActIsTxNoAggregation(struct ieee80211_device* ieee,struct ieee80211_network
{
u8 retValue = 0;
#if (defined RTL8192SU || defined RTL8192SE)
#if defined RTL8192SU
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
if( (KEY_TYPE_WEP104 == ieee->pairwise_key_type) ||
(KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
......@@ -779,7 +777,7 @@ HTIOTActIsDisableTx2SS(struct ieee80211_device* ieee,struct ieee80211_network *n
{
u8 retValue = 0;
#if (defined RTL8192SU || defined RTL8192SE)
#if defined RTL8192SU
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
if( (KEY_TYPE_WEP104 == ieee->pairwise_key_type) ||
(KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
......@@ -799,7 +797,7 @@ HTIOTActIsDisableTx2SS(struct ieee80211_device* ieee,struct ieee80211_network *n
bool HTIOCActAllowPeerAggOnePacket(struct ieee80211_device* ieee,struct ieee80211_network *network)
{
bool retValue = false;
#if defined(RTL8192SE) || defined(RTL8192SU)
#if defined(RTL8192SU)
PRT_HIGH_THROUGHPUT pHTInfo = ieee->pHTInfo;
{
if(pHTInfo->IOTPeer == HT_IOT_PEER_MARVELL)
......
drivers/staging/rtl8192su/r8192S_Efuse.c
View file @ 60083ee0
......@@ -708,12 +708,6 @@ EFUSE_ShadowUpdate(struct net_device* dev)
for (offset = 0; offset < 16; offset++)
{
// Offset 0x18-1F are reserved now!!!
#ifdef RTL8192SE
if(priv->card_8192 == NIC_8192SE){
if (offset == 3)
continue;
}
#endif
word_en = 0x0F;
base = offset * 8;
......@@ -729,12 +723,6 @@ EFUSE_ShadowUpdate(struct net_device* dev)
}
// 2008/12/11 MH HW autoload fail workaround for A/BCUT.
#ifdef RTL8192SE
if (first_pg == TRUE && offset == 1 && (priv->card_8192 == NIC_8192SE))
{
continue;
}
#endif
if (first_pg == TRUE)
{
......@@ -774,21 +762,6 @@ EFUSE_ShadowUpdate(struct net_device* dev)
// 2008/12/01 MH For Efuse HW load bug workarounf method!!!!
// We will force write 0x10EC into address 10&11 after all Efuse content.
//
#ifdef RTL8192SE
if (first_pg == TRUE && (priv->card_8192 == NIC_8192SE))
{
// 2008/12/11 MH Use new method to prevent HW autoload fail.
u8 tmpdata[8];
memcpy(tmpdata, (&priv->EfuseMap[EFUSE_MODIFY_MAP][8]), 8);
efuse_PgPacketWrite(dev, 1, 0x0, tmpdata);
#if 0
u1Byte tmpdata[8] = {0xFF, 0xFF, 0xEC, 0x10, 0xFF, 0xFF, 0xFF, 0xFF};
efuse_PgPacketWrite(pAdapter, 1, 0xD, tmpdata);
#endif
}
#endif
// For warm reboot, we must resume Efuse clock to 500K.
......
drivers/staging/rtl8192su/r8192S_firmware.c
View file @ 60083ee0
......@@ -11,7 +11,7 @@
* NDIS_STATUS_FAILURE - the following initialization process should be terminated
* NDIS_STATUS_SUCCESS - if firmware initialization process success
**************************************************************************************************/
#if defined(RTL8192SE)||defined(RTL8192SU)
#if defined(RTL8192SU)
#include "r8192U.h"
#include "r8192S_firmware.h"
#include <linux/unistd.h>
......@@ -50,9 +50,6 @@ bool FirmwareDownloadCode(struct net_device *dev, u8 * code_virtual_address,u32
u8 bLastIniPkt = 0;
u16 ExtraDescOffset = 0;
#ifdef RTL8192SE
fw_SetRQPN(dev); // For 92SE only
#endif
RT_TRACE(COMP_FIRMWARE, "--->FirmwareDownloadCode()\n" );
......@@ -117,19 +114,6 @@ bool FirmwareDownloadCode(struct net_device *dev, u8 * code_virtual_address,u32
}
#ifdef RTL8192SE
static void fw_SetRQPN(struct net_device *dev)
{
// Only for 92SE HW bug, we have to set RAPN before every FW download
// We can remove the code later.
write_nic_dword(dev, RQPN, 0xffffffff);
write_nic_dword(dev, RQPN+4, 0xffffffff);
write_nic_byte(dev, RQPN+8, 0xff);
write_nic_byte(dev, RQPN+0xB, 0x80);
//#if ((HAL_CODE_BASE == RTL8192_S) && (PLATFORM != PLATFORM_WINDOWS_USB))
} /* fw_SetRQPN */
#endif
RT_STATUS
FirmwareEnableCPU(struct net_device *dev)
......@@ -141,9 +125,6 @@ FirmwareEnableCPU(struct net_device *dev)
u32 iCheckTime = 200;
RT_TRACE(COMP_FIRMWARE, "-->FirmwareEnableCPU()\n" );
#ifdef RTL8192SE
fw_SetRQPN(dev); // For 92SE only
#endif
// Enable CPU.
tmpU1b = read_nic_byte(dev, SYS_CLKR);
write_nic_byte(dev, SYS_CLKR, (tmpU1b|SYS_CPU_CLKSEL)); //AFE source
......@@ -302,10 +283,6 @@ FirmwareCheckReady(struct net_device *dev, u8 LoadFWStatus)
// <Roger_Notes> USB interface will update reserved followings parameters later!!
// 2008.08.28.
//
#ifdef RTL8192SE
//write_nic_dword(dev, RQPN, 0x10101010);
//write_nic_byte(dev, 0xAB, 0x80);
#endif
//
// <Roger_Notes> If right here, we can set TCR/RCR to desired value
......@@ -601,9 +578,6 @@ bool fw_download_code(struct net_device *dev, u8 *code_virtual_address, u32 buff
unsigned char *seg_ptr;
cb_desc *tcb_desc;
u8 bLastIniPkt;
#ifdef RTL8192SE
fw_SetRQPN(dev); // For 92SE only
#endif
#ifndef RTL8192SU
if(buffer_len >= 64000-USB_HWDESC_HEADER_LEN)
......
drivers/staging/rtl8192su/r8192S_firmware.h
View file @ 60083ee0
......@@ -30,12 +30,7 @@
#define MAX_FIRMWARE_CODE_SIZE 0xFF00 // Firmware Local buffer size.
#define RTL8190_CPU_START_OFFSET 0x80
#ifdef RTL8192SE
//It should be double word alignment
#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) 4*(v/4) - 8
#else
#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 - USB_HWDESC_HEADER_LEN)
#endif
//typedef enum _DESC_PACKET_TYPE{
// DESC_PACKET_TYPE_INIT = 0,
......
drivers/staging/rtl8192su/r8192S_hw.h
View file @ 60083ee0
......@@ -1205,106 +1205,6 @@ Default: 00b.
// 8192S EEPROM/EFUSE share register definition.
//----------------------------------------------------------------------------
#ifdef RTL8192SE
//
// 2008/11/05 MH Redefine EEPROM address for 8192SE
// 92SE/SU EEPROM definition seems not the same!!!!!!
// EEPROM MAP REgister Definition!!!! Please refer to 8192SE EEPROM V0.5 2008/10/21
// Update to 8192SE EEPROM V0.6 2008/11/11
//
#define RTL8190_EEPROM_ID 0x8129 // 0-1
#define EEPROM_HPON 0x02 // LDO settings.2-5
#define EEPROM_CLK 0x06 // Clock settings.6-7
#define EEPROM_TESTR 0x08 // SE Test mode.8
#define EEPROM_VID 0x0A // SE Vendor ID.A-B
#define EEPROM_DID 0x0C // SE Device ID. C-D
#define EEPROM_SVID 0x0E // SE Vendor ID.E-F
#define EEPROM_SMID 0x10 // SE PCI Subsystem ID. 10-11
#define EEPROM_MAC_ADDR 0x12 // SEMAC Address. 12-17
#define EEPROM_NODE_ADDRESS_BYTE_0 0x12 // MAC address.
#define EEPROM_PwDiff 0x54 // Difference of gain index between legacy and high throughput OFDM.
//
// 0x20 - 4B EPHY parameter!!!
//
//
#define EEPROM_TxPowerBase 0x50 // Tx Power of serving station.
#define EEPROM_TxPwIndex_CCK_24G 0x5D // 0x50~0x5D Range = 0~0x24//FIXLZM
#define EEPROM_TxPwIndex_OFDM_24G 0x6B // 0x5E~0x6B Range = 0~0x24//FIXLZM
#define EEPROM_TX_PWR_INDEX_RANGE 28 // CCK and OFDM 14 channel
// 2009/01/21 MH Add for SD3 requirement
#define EEPROM_TX_PWR_HT20_DIFF 0x62// HT20 Tx Power Index Difference
#define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference
#define EEPROM_TX_PWR_OFDM_DIFF 0x65// OFDM Tx Power Index Difference
#define EEPROM_TX_PWR_BAND_EDGE 0x67// TX Power offset at band-edge channel
#define TX_PWR_BAND_EDGE_CHK 0x6D// Check if band-edge scheme is enabled
// Oly old EEPROM format support the definition=============================
//
#define EEPROM_TxPwIndex_CCK_24G 0x5D // 0x50~0x5D Range = 0~0x24
#define EEPROM_TxPwIndex_OFDM_24G 0x6B // 0x5E~0x6B Range = 0~0x24
#define EEPROM_HT2T_CH1_A 0x6c //HT 2T path A channel 1 Power Index.
#define EEPROM_HT2T_CH7_A 0x6d //HT 2T path A channel 7 Power Index.
#define EEPROM_HT2T_CH13_A 0x6e //HT 2T path A channel 13 Power Index.
#define EEPROM_HT2T_CH1_B 0x6f //HT 2T path B channel 1 Power Index.
#define EEPROM_HT2T_CH7_B 0x70 //HT 2T path B channel 7 Power Index.
#define EEPROM_HT2T_CH13_B 0x71 //HT 2T path B channel 13 Power Index.
//
#define EEPROM_TSSI_A 0x74 //TSSI value of path A.
#define EEPROM_TSSI_B 0x75 //TSSI value of path B.
//
#define EEPROM_RFInd_PowerDiff 0x76
#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
//
#define EEPROM_ThermalMeter 0x77 // Thermal meter default value.
#define EEPROM_CrystalCap 0x79 // Crystal Cap.
#define EEPROM_ChannelPlan 0x7B // Map of supported channels.
#define EEPROM_Version 0x7C // The EEPROM content version
#define EEPROM_CustomID 0x7A
#define EEPROM_BoardType 0x7E
// 0: 2x2 Green RTL8192GE miniCard (QFN68)
// 1: 1x2 RTL8191SE miniCard (QFN64)
// 2: 2x2 RTL8192SE miniCard (QFN68)
// 3: 1x2 RTL8191SR minicCard(QFN64)
//
// Default Value for EEPROM or EFUSE!!!
//
#define EEPROM_Default_TSSI 0x0
#define EEPROM_Default_TxPowerDiff 0x0
#define EEPROM_Default_CrystalCap 0x5
#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192SE(QFPN68)
#define EEPROM_Default_TxPower 0x1010
#define EEPROM_Default_HT2T_TxPwr 0x10
#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
#define EEPROM_Default_ThermalMeter 0x12
#define EEPROM_Default_AntTxPowerDiff 0x0
#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
#define EEPROM_Default_TxPowerLevel 0x22
#define EEPROM_CHANNEL_PLAN_FCC 0x0
#define EEPROM_CHANNEL_PLAN_IC 0x1
#define EEPROM_CHANNEL_PLAN_ETSI 0x2
#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
#define EEPROM_CHANNEL_PLAN_MKK 0x5
#define EEPROM_CHANNEL_PLAN_MKK1 0x6
#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
#define EEPROM_CHANNEL_PLAN_TELEC 0x8
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_TOSHIBA 0x4
#else
//----------------------------------------------------------------------------
// 8192S EEROM and Compatible E-Fuse definition. Added by Roger, 2008.10.21.
//----------------------------------------------------------------------------
......@@ -1382,7 +1282,6 @@ Default: 00b.
//#define EEPROM_CID_TOSHIBA 0x4
//#define EEPROM_CID_NetCore 0x5
#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108
#endif
//-----------------------------------------------------------------
// 0x2c0 FW Command Control register definition, added by Roger, 2008.11.27.
......
drivers/staging/rtl8192su/r8192S_phy.c
View file @ 60083ee0
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