Merge tag 'renesas-sh-sci2-for-v3.14' of...

Merge tag 'renesas-sh-sci2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup

From Simon Horman:
Second Round of Renesas SH SCI updates for v3.14

* Rework baud rate calculation
* Compute overrun_bit without using baud rate algo
* Remove unused GPIO request code
* Move overrun_bit and error_mask fields out of pdata
* Support resources passed through platform resources
* Don't check IRQ in verify port operation
* Set the UPF_FIXED_PORT flag
* Remove duplicate interrupt check in verify port op
* Simplify baud rate calculation algorithms
* Remove baud rate calculation algorithm 5
* Sort headers alphabetically

* tag 'renesas-sh-sci2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  serial: sh-sci: Rework baud rate calculation
  serial: sh-sci: Compute overrun_bit without using baud rate algo
  serial: sh-sci: Remove unused GPIO request code
  serial: sh-sci: Move overrun_bit and error_mask fields out of pdata
  serial: sh-sci: Support resources passed through platform resources
  serial: sh-sci: Don't check IRQ in verify port operation
  serial: sh-sci: Set the UPF_FIXED_PORT flag
  serial: sh-sci: Remove duplicate interrupt check in verify port op
  serial: sh-sci: Simplify baud rate calculation algorithms
  serial: sh-sci: Remove baud rate calculation algorithm 5
  serial: sh-sci: Sort headers alphabetically
Signed-off-by: Olof Johansson <olof@lixom.net>

drivers/tty/serial/sh-sci.h

@@ -9,7 +9,7 @@
 #define SCxSR_PER(port)		(((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
 #define SCxSR_BRK(port)		(((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
 
-#define SCxSR_ERRORS(port)	(to_sci_port(port)->cfg->error_mask)
+#define SCxSR_ERRORS(port)	(to_sci_port(port)->error_mask)
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
     defined(CONFIG_CPU_SUBTYPE_SH7720) || \

include/linux/serial_sci.h

@@ -11,11 +11,11 @@
 #define SCIx_NOT_SUPPORTED	(-1)
 
 enum {
-	SCBRR_ALGO_1,		/* ((clk + 16 * bps) / (16 * bps) - 1) */
-	SCBRR_ALGO_2,		/* ((clk + 16 * bps) / (32 * bps) - 1) */
-	SCBRR_ALGO_3,		/* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
-	SCBRR_ALGO_4,		/* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
-	SCBRR_ALGO_5,		/* (((clk * 1000 / 32) / bps) - 1) */
+	SCBRR_ALGO_NONE,	/* Compute sampling rate in the driver */
+	SCBRR_ALGO_1,		/* clk / (16 * bps) */
+	SCBRR_ALGO_2,		/* DIV_ROUND_CLOSEST(clk, 32 * bps) - 1 */
+	SCBRR_ALGO_3,		/* clk / (8 * bps) */
+	SCBRR_ALGO_4,		/* DIV_ROUND_CLOSEST(clk, 16 * bps) - 1 */
 	SCBRR_ALGO_6,		/* HSCIF variable sample rate algorithm */
 };
 
@@ -70,17 +70,6 @@ enum {
 	SCIx_MUX_IRQ = SCIx_NR_IRQS,	/* special case */
 };
 
-/* Offsets into the sci_port->gpios array */
-enum {
-	SCIx_SCK,
-	SCIx_RXD,
-	SCIx_TXD,
-	SCIx_CTS,
-	SCIx_RTS,
-
-	SCIx_NR_FNS,
-};
-
 enum {
 	SCIx_PROBE_REGTYPE,
 
@@ -108,10 +97,10 @@ enum {
 }
 
 #define SCIx_IRQ_IS_MUXED(port)			\
-	((port)->cfg->irqs[SCIx_ERI_IRQ] ==	\
-	 (port)->cfg->irqs[SCIx_RXI_IRQ]) ||	\
-	((port)->cfg->irqs[SCIx_ERI_IRQ] &&	\
-	 !(port)->cfg->irqs[SCIx_RXI_IRQ])
+	((port)->irqs[SCIx_ERI_IRQ] ==	\
+	 (port)->irqs[SCIx_RXI_IRQ]) ||	\
+	((port)->irqs[SCIx_ERI_IRQ] &&	\
+	 ((port)->irqs[SCIx_RXI_IRQ] < 0))
 /*
  * SCI register subset common for all port types.
  * Not all registers will exist on all parts.
@@ -142,20 +131,17 @@ struct plat_sci_port_ops {
 struct plat_sci_port {
 	unsigned long	mapbase;		/* resource base */
 	unsigned int	irqs[SCIx_NR_IRQS];	/* ERI, RXI, TXI, BRI */
-	unsigned int	gpios[SCIx_NR_FNS];	/* SCK, RXD, TXD, CTS, RTS */
 	unsigned int	type;			/* SCI / SCIF / IRDA / HSCIF */
 	upf_t		flags;			/* UPF_* flags */
 	unsigned long	capabilities;		/* Port features/capabilities */
 
+	unsigned int	sampling_rate;
 	unsigned int	scbrr_algo_id;		/* SCBRR calculation algo */
 	unsigned int	scscr;			/* SCSCR initialization */
 
 	/*
 	 * Platform overrides if necessary, defaults otherwise.
 	 */
-	int		overrun_bit;
-	unsigned int	error_mask;
-
 	int		port_reg;
 	unsigned char	regshift;
 	unsigned char	regtype;