Commit 620879c9 authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King

[ARM] 4127/1: Flush the prefetch buffer after changing the DACR

The ARM Architecture Reference Manual specifies that a prefetch flush
is needed after changing the DACR register (chapter B2.7.6).
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent dcda7e4b
...@@ -57,6 +57,7 @@ ...@@ -57,6 +57,7 @@
__asm__ __volatile__( \ __asm__ __volatile__( \
"mcr p15, 0, %0, c3, c0 @ set domain" \ "mcr p15, 0, %0, c3, c0 @ set domain" \
: : "r" (x)); \ : : "r" (x)); \
isb(); \
} while (0) } while (0)
#define modify_domain(dom,type) \ #define modify_domain(dom,type) \
......
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