Commit 6402e780 authored by Thierry Reding's avatar Thierry Reding

clk: tegra: Capitalization fixes

HW, XUSB and PLL are abbreviations and should be all-uppercase.
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 9123e3a7
...@@ -1673,7 +1673,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) ...@@ -1673,7 +1673,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
pll_writel(val, PLLE_SS_CTRL, pll); pll_writel(val, PLLE_SS_CTRL, pll);
udelay(1); udelay(1);
/* Enable hw control of xusb brick pll */ /* Enable HW control of XUSB brick PLL */
val = pll_readl_misc(pll); val = pll_readl_misc(pll);
val &= ~PLLE_MISC_IDDQ_SW_CTRL; val &= ~PLLE_MISC_IDDQ_SW_CTRL;
pll_writel_misc(val, pll); pll_writel_misc(val, pll);
...@@ -1696,7 +1696,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) ...@@ -1696,7 +1696,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
pll_writel(val, XUSBIO_PLL_CFG0, pll); pll_writel(val, XUSBIO_PLL_CFG0, pll);
/* Enable hw control of SATA pll */ /* Enable HW control of SATA PLL */
val = pll_readl(SATA_PLL_CFG0, pll); val = pll_readl(SATA_PLL_CFG0, pll);
val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment