Commit 651659c1 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman

staging: comedi: me_daq: fix me_ai_insn_read()

The comedi core expects (*insn_read) functions to return insn->n data
values. Refactor the function to work like the core expects. For
aesthetics, use the comedi_offset_munge() helper to munge the 2's
complement data.

This also fixes a minor issue when comedi_timeout() times out. Currently
this function just returns which leaves the ADC mode programmed for
software triggering. With the refactor the ADC mode is always disabled
when the function exits. This allows removing the unnecessary steps to
"stop any running conversions" at the start of the function.
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 8a844a91
...@@ -243,8 +243,9 @@ static int me_ai_insn_read(struct comedi_device *dev, ...@@ -243,8 +243,9 @@ static int me_ai_insn_read(struct comedi_device *dev,
unsigned int chan = CR_CHAN(insn->chanspec); unsigned int chan = CR_CHAN(insn->chanspec);
unsigned int range = CR_RANGE(insn->chanspec); unsigned int range = CR_RANGE(insn->chanspec);
unsigned int aref = CR_AREF(insn->chanspec); unsigned int aref = CR_AREF(insn->chanspec);
unsigned short val; unsigned int val;
int ret; int ret = 0;
int i;
/* /*
* For differential operation, there are only 8 input channels * For differential operation, there are only 8 input channels
...@@ -255,10 +256,6 @@ static int me_ai_insn_read(struct comedi_device *dev, ...@@ -255,10 +256,6 @@ static int me_ai_insn_read(struct comedi_device *dev,
return -EINVAL; return -EINVAL;
} }
/* stop any running conversion */
devpriv->ctrl1 &= ~ME_CTRL1_ADC_MODE_MASK;
writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);
/* clear chanlist and ad fifo */ /* clear chanlist and ad fifo */
devpriv->ctrl2 &= ~(ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA); devpriv->ctrl2 &= ~(ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA);
writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
...@@ -281,24 +278,27 @@ static int me_ai_insn_read(struct comedi_device *dev, ...@@ -281,24 +278,27 @@ static int me_ai_insn_read(struct comedi_device *dev,
devpriv->ctrl1 |= ME_CTRL1_ADC_MODE_SOFT_TRIG; devpriv->ctrl1 |= ME_CTRL1_ADC_MODE_SOFT_TRIG;
writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);
/* start ai conversion */ for (i = 0; i < insn->n; i++) {
readw(dev->mmio + ME_CTRL1_REG); /* start ai conversion */
readw(dev->mmio + ME_CTRL1_REG);
/* wait for ADC fifo not empty flag */ /* wait for ADC fifo not empty flag */
ret = comedi_timeout(dev, s, insn, me_ai_eoc, 0); ret = comedi_timeout(dev, s, insn, me_ai_eoc, 0);
if (ret) if (ret)
return ret; break;
/* get value from ADC fifo */
val = readw(dev->mmio + ME_AI_FIFO_REG) & s->maxdata;
/* get value from ADC fifo */ /* munge 2's complement value to offset binary */
val = readw(dev->mmio + ME_AI_FIFO_REG); data[i] = comedi_offset_munge(s, val);
val = (val ^ 0x800) & 0x0fff; }
data[0] = val;
/* stop any running conversion */ /* stop any running conversion */
devpriv->ctrl1 &= ~ME_CTRL1_ADC_MODE_MASK; devpriv->ctrl1 &= ~ME_CTRL1_ADC_MODE_MASK;
writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);
return 1; return ret ? ret : insn->n;
} }
static int me_ao_insn_write(struct comedi_device *dev, static int me_ao_insn_write(struct comedi_device *dev,
......
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