Commit 656409bb authored by Imre Deak's avatar Imre Deak Committed by Lucas De Marchi

drm/i915/tgl: Add power well support

The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the following:

- Transcoder#EDP removed from power well#1 (Transcoder#A used in
  low-power mode instead)
- Transcoder#A is now backed by power well#1 instead of power well#3
- The DDI#B/C combo PHY ports are now backed by power well#1 instead of
  power well#3
- New power well#5 added for pipe#D functionality (TODO)
- 2 additional TC ports (TC#5-6) backed by power well#3, 2 port
  specific IO power wells (only for the non-TBT modes) and 4 port
  specific AUX power wells (2-2 for TBT vs. non-TBT modes)
- Power well#2 backs now VDSC/joining for pipe#A instead of VDSC for
  eDP and MIPI DSI (TODO)

On TGL Port DDI#C changed to be a combo PHY (native DP/HDMI) and
BSpec has renamed ports DDI#D-F to TC#4-6 respectively. Thus on ICL we
have the following naming for ports:

- Combo PHYs (native DP/HDMI):
  DDI#A-B
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
  DDI#C-F

Starting from GEN 12 we have the following naming for ports:
- Combo PHYs (native DP/HDMI):
  DDI#A-C
- TBT/non-TBT (TC altmode, native DP/HDMI) PHYs:
  DDI TC#1-6

To save some space in the power domain enum the power domain naming in
the driver reflects the above change, that is power domains TC#1-3 are
added as aliases for DDI#D-F and new power domains are reserved for
TC#4-6.

v2 (Lucas):
  - Separate out the bits and definitions for TGL from the ICL ones.
    Fix use of TRANSCODER_EDP_VDSC, that is now the correct define since
    we don't define TRANSCODER_A_VDSC power domain to spare a one bit in
    the bitmask (suggested by Ville)
v3 (Lucas):
  - Fix missing squashes on v2
  - Rebase on renamed TRANSCODER_EDP_VDSC

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-9-lucas.demarchi@intel.com
parent 276199e6
...@@ -33,14 +33,29 @@ enum intel_display_power_domain { ...@@ -33,14 +33,29 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_B_LANES, POWER_DOMAIN_PORT_DDI_B_LANES,
POWER_DOMAIN_PORT_DDI_C_LANES, POWER_DOMAIN_PORT_DDI_C_LANES,
POWER_DOMAIN_PORT_DDI_D_LANES, POWER_DOMAIN_PORT_DDI_D_LANES,
POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES,
POWER_DOMAIN_PORT_DDI_E_LANES, POWER_DOMAIN_PORT_DDI_E_LANES,
POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES,
POWER_DOMAIN_PORT_DDI_F_LANES, POWER_DOMAIN_PORT_DDI_F_LANES,
POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES,
POWER_DOMAIN_PORT_DDI_TC4_LANES,
POWER_DOMAIN_PORT_DDI_TC5_LANES,
POWER_DOMAIN_PORT_DDI_TC6_LANES,
POWER_DOMAIN_PORT_DDI_A_IO, POWER_DOMAIN_PORT_DDI_A_IO,
POWER_DOMAIN_PORT_DDI_B_IO, POWER_DOMAIN_PORT_DDI_B_IO,
POWER_DOMAIN_PORT_DDI_C_IO, POWER_DOMAIN_PORT_DDI_C_IO,
POWER_DOMAIN_PORT_DDI_D_IO, POWER_DOMAIN_PORT_DDI_D_IO,
POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
POWER_DOMAIN_PORT_DDI_E_IO, POWER_DOMAIN_PORT_DDI_E_IO,
POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
POWER_DOMAIN_PORT_DDI_F_IO, POWER_DOMAIN_PORT_DDI_F_IO,
POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
POWER_DOMAIN_PORT_DDI_G_IO,
POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
POWER_DOMAIN_PORT_DDI_H_IO,
POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
POWER_DOMAIN_PORT_DDI_I_IO,
POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
POWER_DOMAIN_PORT_DSI, POWER_DOMAIN_PORT_DSI,
POWER_DOMAIN_PORT_CRT, POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_PORT_OTHER, POWER_DOMAIN_PORT_OTHER,
...@@ -50,13 +65,21 @@ enum intel_display_power_domain { ...@@ -50,13 +65,21 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_B, POWER_DOMAIN_AUX_B,
POWER_DOMAIN_AUX_C, POWER_DOMAIN_AUX_C,
POWER_DOMAIN_AUX_D, POWER_DOMAIN_AUX_D,
POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
POWER_DOMAIN_AUX_E, POWER_DOMAIN_AUX_E,
POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
POWER_DOMAIN_AUX_F, POWER_DOMAIN_AUX_F,
POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
POWER_DOMAIN_AUX_TC4,
POWER_DOMAIN_AUX_TC5,
POWER_DOMAIN_AUX_TC6,
POWER_DOMAIN_AUX_IO_A, POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_AUX_TBT1, POWER_DOMAIN_AUX_TBT1,
POWER_DOMAIN_AUX_TBT2, POWER_DOMAIN_AUX_TBT2,
POWER_DOMAIN_AUX_TBT3, POWER_DOMAIN_AUX_TBT3,
POWER_DOMAIN_AUX_TBT4, POWER_DOMAIN_AUX_TBT4,
POWER_DOMAIN_AUX_TBT5,
POWER_DOMAIN_AUX_TBT6,
POWER_DOMAIN_GMBUS, POWER_DOMAIN_GMBUS,
POWER_DOMAIN_MODESET, POWER_DOMAIN_MODESET,
POWER_DOMAIN_GT_IRQ, POWER_DOMAIN_GT_IRQ,
...@@ -229,7 +252,8 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume); ...@@ -229,7 +252,8 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
void bxt_display_core_uninit(struct drm_i915_private *dev_priv); void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
const char * const char *
intel_display_power_domain_str(enum intel_display_power_domain domain); intel_display_power_domain_str(struct drm_i915_private *i915,
enum intel_display_power_domain domain);
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain); enum intel_display_power_domain domain);
......
...@@ -2466,7 +2466,8 @@ static int i915_power_domain_info(struct seq_file *m, void *unused) ...@@ -2466,7 +2466,8 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
for_each_power_domain(power_domain, power_well->desc->domains) for_each_power_domain(power_domain, power_well->desc->domains)
seq_printf(m, " %-23s %d\n", seq_printf(m, " %-23s %d\n",
intel_display_power_domain_str(power_domain), intel_display_power_domain_str(dev_priv,
power_domain),
power_domains->domain_use_count[power_domain]); power_domains->domain_use_count[power_domain]);
} }
......
...@@ -9147,7 +9147,7 @@ enum { ...@@ -9147,7 +9147,7 @@ enum {
#define GLK_PW_CTL_IDX_DDI_A 1 #define GLK_PW_CTL_IDX_DDI_A 1
#define SKL_PW_CTL_IDX_MISC_IO 0 #define SKL_PW_CTL_IDX_MISC_IO 0
/* ICL - power wells */ /* ICL/TGL - power wells */
#define ICL_PW_CTL_IDX_PW_4 3 #define ICL_PW_CTL_IDX_PW_4 3
#define ICL_PW_CTL_IDX_PW_3 2 #define ICL_PW_CTL_IDX_PW_3 2
#define ICL_PW_CTL_IDX_PW_2 1 #define ICL_PW_CTL_IDX_PW_2 1
...@@ -9156,13 +9156,25 @@ enum { ...@@ -9156,13 +9156,25 @@ enum {
#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
#define TGL_PW_CTL_IDX_AUX_TBT6 14
#define TGL_PW_CTL_IDX_AUX_TBT5 13
#define TGL_PW_CTL_IDX_AUX_TBT4 12
#define ICL_PW_CTL_IDX_AUX_TBT4 11 #define ICL_PW_CTL_IDX_AUX_TBT4 11
#define TGL_PW_CTL_IDX_AUX_TBT3 11
#define ICL_PW_CTL_IDX_AUX_TBT3 10 #define ICL_PW_CTL_IDX_AUX_TBT3 10
#define TGL_PW_CTL_IDX_AUX_TBT2 10
#define ICL_PW_CTL_IDX_AUX_TBT2 9 #define ICL_PW_CTL_IDX_AUX_TBT2 9
#define TGL_PW_CTL_IDX_AUX_TBT1 9
#define ICL_PW_CTL_IDX_AUX_TBT1 8 #define ICL_PW_CTL_IDX_AUX_TBT1 8
#define TGL_PW_CTL_IDX_AUX_TC6 8
#define TGL_PW_CTL_IDX_AUX_TC5 7
#define TGL_PW_CTL_IDX_AUX_TC4 6
#define ICL_PW_CTL_IDX_AUX_F 5 #define ICL_PW_CTL_IDX_AUX_F 5
#define TGL_PW_CTL_IDX_AUX_TC3 5
#define ICL_PW_CTL_IDX_AUX_E 4 #define ICL_PW_CTL_IDX_AUX_E 4
#define TGL_PW_CTL_IDX_AUX_TC2 4
#define ICL_PW_CTL_IDX_AUX_D 3 #define ICL_PW_CTL_IDX_AUX_D 3
#define TGL_PW_CTL_IDX_AUX_TC1 3
#define ICL_PW_CTL_IDX_AUX_C 2 #define ICL_PW_CTL_IDX_AUX_C 2
#define ICL_PW_CTL_IDX_AUX_B 1 #define ICL_PW_CTL_IDX_AUX_B 1
#define ICL_PW_CTL_IDX_AUX_A 0 #define ICL_PW_CTL_IDX_AUX_A 0
...@@ -9170,9 +9182,15 @@ enum { ...@@ -9170,9 +9182,15 @@ enum {
#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
#define TGL_PW_CTL_IDX_DDI_TC6 8
#define TGL_PW_CTL_IDX_DDI_TC5 7
#define TGL_PW_CTL_IDX_DDI_TC4 6
#define ICL_PW_CTL_IDX_DDI_F 5 #define ICL_PW_CTL_IDX_DDI_F 5
#define TGL_PW_CTL_IDX_DDI_TC3 5
#define ICL_PW_CTL_IDX_DDI_E 4 #define ICL_PW_CTL_IDX_DDI_E 4
#define TGL_PW_CTL_IDX_DDI_TC2 4
#define ICL_PW_CTL_IDX_DDI_D 3 #define ICL_PW_CTL_IDX_DDI_D 3
#define TGL_PW_CTL_IDX_DDI_TC1 3
#define ICL_PW_CTL_IDX_DDI_C 2 #define ICL_PW_CTL_IDX_DDI_C 2
#define ICL_PW_CTL_IDX_DDI_B 1 #define ICL_PW_CTL_IDX_DDI_B 1
#define ICL_PW_CTL_IDX_DDI_A 0 #define ICL_PW_CTL_IDX_DDI_A 0
......
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