Commit 6911498d authored by Shawn Guo's avatar Shawn Guo

drm: zte: add VGA driver support

It adds VGA driver support, which needs to configure corresponding VOU
interface in RGB_888 format, and thus the following changes are needed
on zx_vou.

 - Rename the CSC block of Graphic Layer a bit to make it more specific,
   and add CSC of Channel to support RGB output.
 - Bypass Dither block for RGB output.
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: default avatarSean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1491910226-7831-1-git-send-email-shawnguo@kernel.org
parent cd4b2983
...@@ -3,6 +3,7 @@ zxdrm-y := \ ...@@ -3,6 +3,7 @@ zxdrm-y := \
zx_hdmi.o \ zx_hdmi.o \
zx_plane.o \ zx_plane.o \
zx_tvenc.o \ zx_tvenc.o \
zx_vga.o \
zx_vou.o zx_vou.o
obj-$(CONFIG_DRM_ZTE) += zxdrm.o obj-$(CONFIG_DRM_ZTE) += zxdrm.o
...@@ -233,6 +233,7 @@ static struct platform_driver *drivers[] = { ...@@ -233,6 +233,7 @@ static struct platform_driver *drivers[] = {
&zx_crtc_driver, &zx_crtc_driver,
&zx_hdmi_driver, &zx_hdmi_driver,
&zx_tvenc_driver, &zx_tvenc_driver,
&zx_vga_driver,
&zx_drm_platform_driver, &zx_drm_platform_driver,
}; };
......
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
extern struct platform_driver zx_crtc_driver; extern struct platform_driver zx_crtc_driver;
extern struct platform_driver zx_hdmi_driver; extern struct platform_driver zx_hdmi_driver;
extern struct platform_driver zx_tvenc_driver; extern struct platform_driver zx_tvenc_driver;
extern struct platform_driver zx_vga_driver;
static inline u32 zx_readl(void __iomem *reg) static inline u32 zx_readl(void __iomem *reg)
{ {
......
This diff is collapsed.
/*
* Copyright (C) 2017 Sanechips Technology Co., Ltd.
* Copyright 2017 Linaro Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ZX_VGA_REGS_H__
#define __ZX_VGA_REGS_H__
#define VGA_CMD_CFG 0x04
#define VGA_CMD_TRANS BIT(6)
#define VGA_CMD_COMBO BIT(5)
#define VGA_CMD_RW BIT(4)
#define VGA_SUB_ADDR 0x0c
#define VGA_DEVICE_ADDR 0x10
#define VGA_CLK_DIV_FS 0x14
#define VGA_RXF_CTRL 0x20
#define VGA_RX_FIFO_CLEAR BIT(7)
#define VGA_DATA 0x24
#define VGA_I2C_STATUS 0x28
#define VGA_DEVICE_DISCONNECTED BIT(7)
#define VGA_DEVICE_CONNECTED BIT(6)
#define VGA_CLEAR_IRQ BIT(4)
#define VGA_TRANS_DONE BIT(0)
#define VGA_RXF_STATUS 0x30
#define VGA_RXF_COUNT_SHIFT 2
#define VGA_RXF_COUNT_MASK GENMASK(7, 2)
#define VGA_AUTO_DETECT_PARA 0x34
#define VGA_AUTO_DETECT_SEL 0x38
#define VGA_DETECT_SEL_HAS_DEVICE BIT(1)
#define VGA_DETECT_SEL_NO_DEVICE BIT(0)
#endif /* __ZX_VGA_REGS_H__ */
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
#include <drm/drm_plane_helper.h> #include <drm/drm_plane_helper.h>
#include <drm/drmP.h> #include <drm/drmP.h>
#include "zx_common_regs.h"
#include "zx_drm_drv.h" #include "zx_drm_drv.h"
#include "zx_plane.h" #include "zx_plane.h"
#include "zx_vou.h" #include "zx_vou.h"
...@@ -122,6 +123,8 @@ struct zx_crtc { ...@@ -122,6 +123,8 @@ struct zx_crtc {
struct drm_plane *primary; struct drm_plane *primary;
struct zx_vou_hw *vou; struct zx_vou_hw *vou;
void __iomem *chnreg; void __iomem *chnreg;
void __iomem *chncsc;
void __iomem *dither;
const struct zx_crtc_regs *regs; const struct zx_crtc_regs *regs;
const struct zx_crtc_bits *bits; const struct zx_crtc_bits *bits;
enum vou_chn_type chn_type; enum vou_chn_type chn_type;
...@@ -204,6 +207,11 @@ static struct vou_inf vou_infs[] = { ...@@ -204,6 +207,11 @@ static struct vou_inf vou_infs[] = {
.clocks_en_bits = BIT(15), .clocks_en_bits = BIT(15),
.clocks_sel_bits = BIT(11) | BIT(0), .clocks_sel_bits = BIT(11) | BIT(0),
}, },
[VOU_VGA] = {
.data_sel = VOU_RGB_888,
.clocks_en_bits = BIT(1),
.clocks_sel_bits = BIT(10),
},
}; };
static inline struct zx_vou_hw *crtc_to_vou(struct drm_crtc *crtc) static inline struct zx_vou_hw *crtc_to_vou(struct drm_crtc *crtc)
...@@ -227,9 +235,26 @@ void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc) ...@@ -227,9 +235,26 @@ void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc)
struct zx_crtc *zcrtc = to_zx_crtc(crtc); struct zx_crtc *zcrtc = to_zx_crtc(crtc);
struct zx_vou_hw *vou = zcrtc->vou; struct zx_vou_hw *vou = zcrtc->vou;
struct vou_inf *inf = &vou_infs[id]; struct vou_inf *inf = &vou_infs[id];
void __iomem *dither = zcrtc->dither;
void __iomem *csc = zcrtc->chncsc;
bool is_main = zcrtc->chn_type == VOU_CHN_MAIN; bool is_main = zcrtc->chn_type == VOU_CHN_MAIN;
u32 data_sel_shift = id << 1; u32 data_sel_shift = id << 1;
if (inf->data_sel != VOU_YUV444) {
/* Enable channel CSC for RGB output */
zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,
CSC_BT709_IMAGE_YCBCR2RGB << CSC_COV_MODE_SHIFT);
zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE,
CSC_WORK_ENABLE);
/* Bypass Dither block for RGB output */
zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS,
DITHER_BYSPASS);
} else {
zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, 0);
zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS, 0);
}
/* Select data format */ /* Select data format */
zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift, zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,
inf->data_sel << data_sel_shift); inf->data_sel << data_sel_shift);
...@@ -525,20 +550,24 @@ static int zx_crtc_init(struct drm_device *drm, struct zx_vou_hw *vou, ...@@ -525,20 +550,24 @@ static int zx_crtc_init(struct drm_device *drm, struct zx_vou_hw *vou,
if (chn_type == VOU_CHN_MAIN) { if (chn_type == VOU_CHN_MAIN) {
zplane->layer = vou->osd + MAIN_GL_OFFSET; zplane->layer = vou->osd + MAIN_GL_OFFSET;
zplane->csc = vou->osd + MAIN_CSC_OFFSET; zplane->csc = vou->osd + MAIN_GL_CSC_OFFSET;
zplane->hbsc = vou->osd + MAIN_HBSC_OFFSET; zplane->hbsc = vou->osd + MAIN_HBSC_OFFSET;
zplane->rsz = vou->otfppu + MAIN_RSZ_OFFSET; zplane->rsz = vou->otfppu + MAIN_RSZ_OFFSET;
zplane->bits = &zx_gl_bits[0]; zplane->bits = &zx_gl_bits[0];
zcrtc->chnreg = vou->osd + OSD_MAIN_CHN; zcrtc->chnreg = vou->osd + OSD_MAIN_CHN;
zcrtc->chncsc = vou->osd + MAIN_CHN_CSC_OFFSET;
zcrtc->dither = vou->osd + MAIN_DITHER_OFFSET;
zcrtc->regs = &main_crtc_regs; zcrtc->regs = &main_crtc_regs;
zcrtc->bits = &main_crtc_bits; zcrtc->bits = &main_crtc_bits;
} else { } else {
zplane->layer = vou->osd + AUX_GL_OFFSET; zplane->layer = vou->osd + AUX_GL_OFFSET;
zplane->csc = vou->osd + AUX_CSC_OFFSET; zplane->csc = vou->osd + AUX_GL_CSC_OFFSET;
zplane->hbsc = vou->osd + AUX_HBSC_OFFSET; zplane->hbsc = vou->osd + AUX_HBSC_OFFSET;
zplane->rsz = vou->otfppu + AUX_RSZ_OFFSET; zplane->rsz = vou->otfppu + AUX_RSZ_OFFSET;
zplane->bits = &zx_gl_bits[1]; zplane->bits = &zx_gl_bits[1];
zcrtc->chnreg = vou->osd + OSD_AUX_CHN; zcrtc->chnreg = vou->osd + OSD_AUX_CHN;
zcrtc->chncsc = vou->osd + AUX_CHN_CSC_OFFSET;
zcrtc->dither = vou->osd + AUX_DITHER_OFFSET;
zcrtc->regs = &aux_crtc_regs; zcrtc->regs = &aux_crtc_regs;
zcrtc->bits = &aux_crtc_bits; zcrtc->bits = &aux_crtc_bits;
} }
......
...@@ -13,13 +13,17 @@ ...@@ -13,13 +13,17 @@
/* Sub-module offset */ /* Sub-module offset */
#define MAIN_GL_OFFSET 0x130 #define MAIN_GL_OFFSET 0x130
#define MAIN_CSC_OFFSET 0x580 #define MAIN_GL_CSC_OFFSET 0x580
#define MAIN_CHN_CSC_OFFSET 0x6c0
#define MAIN_HBSC_OFFSET 0x820 #define MAIN_HBSC_OFFSET 0x820
#define MAIN_DITHER_OFFSET 0x960
#define MAIN_RSZ_OFFSET 0x600 /* OTFPPU sub-module */ #define MAIN_RSZ_OFFSET 0x600 /* OTFPPU sub-module */
#define AUX_GL_OFFSET 0x200 #define AUX_GL_OFFSET 0x200
#define AUX_CSC_OFFSET 0x5d0 #define AUX_GL_CSC_OFFSET 0x5d0
#define AUX_CHN_CSC_OFFSET 0x710
#define AUX_HBSC_OFFSET 0x860 #define AUX_HBSC_OFFSET 0x860
#define AUX_DITHER_OFFSET 0x970
#define AUX_RSZ_OFFSET 0x800 #define AUX_RSZ_OFFSET 0x800
#define OSD_VL0_OFFSET 0x040 #define OSD_VL0_OFFSET 0x040
...@@ -78,6 +82,10 @@ ...@@ -78,6 +82,10 @@
#define CHN_INTERLACE_BUF_CTRL 0x24 #define CHN_INTERLACE_BUF_CTRL 0x24
#define CHN_INTERLACE_EN BIT(2) #define CHN_INTERLACE_EN BIT(2)
/* Dither registers */
#define OSD_DITHER_CTRL0 0x00
#define DITHER_BYSPASS BIT(31)
/* TIMING_CTRL registers */ /* TIMING_CTRL registers */
#define TIMING_TC_ENABLE 0x04 #define TIMING_TC_ENABLE 0x04
#define AUX_TC_EN BIT(1) #define AUX_TC_EN BIT(1)
......
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