Commit 69fe3fd7 authored by Ayaz Abdulla's avatar Ayaz Abdulla Committed by Jeff Garzik

[PATCH] forcedeth config: module parameters

This patch adds (and modifies) module parameter support.
Signed-Off-By: default avatarAyaz Abdulla <aabdulla@nvidia.com>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 9589c77a
...@@ -761,8 +761,10 @@ static int max_interrupt_work = 5; ...@@ -761,8 +761,10 @@ static int max_interrupt_work = 5;
* Throughput Mode: Every tx and rx packet will generate an interrupt. * Throughput Mode: Every tx and rx packet will generate an interrupt.
* CPU Mode: Interrupts are controlled by a timer. * CPU Mode: Interrupts are controlled by a timer.
*/ */
#define NV_OPTIMIZATION_MODE_THROUGHPUT 0 enum {
#define NV_OPTIMIZATION_MODE_CPU 1 NV_OPTIMIZATION_MODE_THROUGHPUT,
NV_OPTIMIZATION_MODE_CPU
};
static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
/* /*
...@@ -775,14 +777,31 @@ static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; ...@@ -775,14 +777,31 @@ static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
static int poll_interval = -1; static int poll_interval = -1;
/* /*
* Disable MSI interrupts * MSI interrupts
*/ */
static int disable_msi = 0; enum {
NV_MSI_INT_DISABLED,
NV_MSI_INT_ENABLED
};
static int msi = NV_MSI_INT_ENABLED;
/* /*
* Disable MSIX interrupts * MSIX interrupts
*/ */
static int disable_msix = 0; enum {
NV_MSIX_INT_DISABLED,
NV_MSIX_INT_ENABLED
};
static int msix = NV_MSIX_INT_ENABLED;
/*
* DMA 64bit
*/
enum {
NV_DMA_64BIT_DISABLED,
NV_DMA_64BIT_ENABLED
};
static int dma_64bit = NV_DMA_64BIT_ENABLED;
static inline struct fe_priv *get_nvpriv(struct net_device *dev) static inline struct fe_priv *get_nvpriv(struct net_device *dev)
{ {
...@@ -4115,16 +4134,18 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i ...@@ -4115,16 +4134,18 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
/* packet format 3: supports 40-bit addressing */ /* packet format 3: supports 40-bit addressing */
np->desc_ver = DESC_VER_3; np->desc_ver = DESC_VER_3;
np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) { if (dma_64bit) {
printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n", if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
pci_name(pci_dev)); printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
} else { pci_name(pci_dev));
dev->features |= NETIF_F_HIGHDMA; } else {
printk(KERN_INFO "forcedeth: using HIGHDMA\n"); dev->features |= NETIF_F_HIGHDMA;
} printk(KERN_INFO "forcedeth: using HIGHDMA\n");
if (pci_set_consistent_dma_mask(pci_dev, 0x0000007fffffffffULL)) { }
printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed for device %s.\n", if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
pci_name(pci_dev)); printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
pci_name(pci_dev));
}
} }
} else if (id->driver_data & DEV_HAS_LARGEDESC) { } else if (id->driver_data & DEV_HAS_LARGEDESC) {
/* packet format 2: supports jumbo frames */ /* packet format 2: supports jumbo frames */
...@@ -4157,10 +4178,10 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i ...@@ -4157,10 +4178,10 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
} }
np->msi_flags = 0; np->msi_flags = 0;
if ((id->driver_data & DEV_HAS_MSI) && !disable_msi) { if ((id->driver_data & DEV_HAS_MSI) && msi) {
np->msi_flags |= NV_MSI_CAPABLE; np->msi_flags |= NV_MSI_CAPABLE;
} }
if ((id->driver_data & DEV_HAS_MSI_X) && !disable_msix) { if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
np->msi_flags |= NV_MSI_X_CAPABLE; np->msi_flags |= NV_MSI_X_CAPABLE;
} }
...@@ -4473,10 +4494,12 @@ module_param(optimization_mode, int, 0); ...@@ -4473,10 +4494,12 @@ module_param(optimization_mode, int, 0);
MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer."); MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
module_param(poll_interval, int, 0); module_param(poll_interval, int, 0);
MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535."); MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
module_param(disable_msi, int, 0); module_param(msi, int, 0);
MODULE_PARM_DESC(disable_msi, "Disable MSI interrupts by setting to 1."); MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
module_param(disable_msix, int, 0); module_param(msix, int, 0);
MODULE_PARM_DESC(disable_msix, "Disable MSIX interrupts by setting to 1."); MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
module_param(dma_64bit, int, 0);
MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
......
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