Commit 6bb5d75e authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Greg Kroah-Hartman

serial: 8250_lpss: move Quark code from PCI driver

Intel Quark has DesignWare UART. Move the code from 8250_pci to 8250_lpss.
Reviewed-by: default avatarBryan O'Donoghue <pure.logic@nexus-software.ie>
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: default avatarBryan O'Donoghue <pure.logic@nexus-software.ie>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a13e19cf
...@@ -19,6 +19,8 @@ ...@@ -19,6 +19,8 @@
#include "8250.h" #include "8250.h"
#define PCI_DEVICE_ID_INTEL_QRK_UARTx 0x0936
#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
...@@ -166,6 +168,9 @@ static int lpss8250_dma_setup(struct lpss8250 *lpss, struct uart_8250_port *port ...@@ -166,6 +168,9 @@ static int lpss8250_dma_setup(struct lpss8250 *lpss, struct uart_8250_port *port
struct dw_dma_slave *rx_param, *tx_param; struct dw_dma_slave *rx_param, *tx_param;
struct device *dev = port->port.dev; struct device *dev = port->port.dev;
if (!lpss->dma_param.dma_dev)
return 0;
rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL); rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
if (!rx_param) if (!rx_param)
return -ENOMEM; return -ENOMEM;
...@@ -253,9 +258,15 @@ static const struct lpss8250_board byt_board = { ...@@ -253,9 +258,15 @@ static const struct lpss8250_board byt_board = {
.setup = byt_serial_setup, .setup = byt_serial_setup,
}; };
static const struct lpss8250_board qrk_board = {
.freq = 44236800,
.base_baud = 2764800,
};
#define LPSS_DEVICE(id, board) { PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&board } #define LPSS_DEVICE(id, board) { PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&board }
static const struct pci_device_id pci_ids[] = { static const struct pci_device_id pci_ids[] = {
LPSS_DEVICE(PCI_DEVICE_ID_INTEL_QRK_UARTx, qrk_board),
LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BYT_UART1, byt_board), LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BYT_UART1, byt_board),
LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BYT_UART2, byt_board), LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BYT_UART2, byt_board),
LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BSW_UART1, byt_board), LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BSW_UART1, byt_board),
......
...@@ -1776,7 +1776,6 @@ pci_wch_ch38x_setup(struct serial_private *priv, ...@@ -1776,7 +1776,6 @@ pci_wch_ch38x_setup(struct serial_private *priv,
#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
#define PCI_VENDOR_ID_SUNIX 0x1fd4 #define PCI_VENDOR_ID_SUNIX 0x1fd4
#define PCI_DEVICE_ID_SUNIX_1999 0x1999 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
...@@ -2755,7 +2754,6 @@ enum pci_board_num_t { ...@@ -2755,7 +2754,6 @@ enum pci_board_num_t {
pbn_ADDIDATA_PCIe_4_3906250, pbn_ADDIDATA_PCIe_4_3906250,
pbn_ADDIDATA_PCIe_8_3906250, pbn_ADDIDATA_PCIe_8_3906250,
pbn_ce4100_1_115200, pbn_ce4100_1_115200,
pbn_qrk,
pbn_omegapci, pbn_omegapci,
pbn_NETMOS9900_2s_115200, pbn_NETMOS9900_2s_115200,
pbn_brcm_trumanage, pbn_brcm_trumanage,
...@@ -3531,12 +3529,6 @@ static struct pciserial_board pci_boards[] = { ...@@ -3531,12 +3529,6 @@ static struct pciserial_board pci_boards[] = {
.base_baud = 921600, .base_baud = 921600,
.reg_shift = 2, .reg_shift = 2,
}, },
[pbn_qrk] = {
.flags = FL_BASE0,
.num_ports = 1,
.base_baud = 2764800,
.reg_shift = 2,
},
[pbn_omegapci] = { [pbn_omegapci] = {
.flags = FL_BASE0, .flags = FL_BASE0,
.num_ports = 8, .num_ports = 8,
...@@ -3650,6 +3642,7 @@ static const struct pci_device_id blacklist[] = { ...@@ -3650,6 +3642,7 @@ static const struct pci_device_id blacklist[] = {
{ PCI_VDEVICE(INTEL, 0x19d8), }, { PCI_VDEVICE(INTEL, 0x19d8), },
/* Intel platforms with DesignWare UART */ /* Intel platforms with DesignWare UART */
{ PCI_VDEVICE(INTEL, 0x0936), },
{ PCI_VDEVICE(INTEL, 0x0f0a), }, { PCI_VDEVICE(INTEL, 0x0f0a), },
{ PCI_VDEVICE(INTEL, 0x0f0c), }, { PCI_VDEVICE(INTEL, 0x0f0c), },
{ PCI_VDEVICE(INTEL, 0x228a), }, { PCI_VDEVICE(INTEL, 0x228a), },
...@@ -5322,12 +5315,6 @@ static struct pci_device_id serial_pci_tbl[] = { ...@@ -5322,12 +5315,6 @@ static struct pci_device_id serial_pci_tbl[] = {
PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ce4100_1_115200 }, pbn_ce4100_1_115200 },
/*
* Intel Quark x1000
*/
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_qrk },
/* /*
* Cronyx Omega PCI * Cronyx Omega PCI
*/ */
......
...@@ -415,6 +415,7 @@ config SERIAL_8250_LPSS ...@@ -415,6 +415,7 @@ config SERIAL_8250_LPSS
present on the UART found on various Intel platforms such as: present on the UART found on various Intel platforms such as:
- Intel Baytrail SoC - Intel Baytrail SoC
- Intel Braswell SoC - Intel Braswell SoC
- Intel Quark X1000 SoC
config SERIAL_8250_MID config SERIAL_8250_MID
tristate "Support for serial ports on Intel MID platforms" if EXPERT tristate "Support for serial ports on Intel MID platforms" if EXPERT
......
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