Commit 6d011d50 authored by Mohan Kumar's avatar Mohan Kumar Committed by Takashi Iwai

ALSA: hda: Clear RIRB status before reading WP

RIRB interrupt status getting cleared after the write pointer is read
causes a race condition, where last response(s) into RIRB may remain
unserviced by IRQ, eventually causing azx_rirb_get_response to fall
back to polling mode. Clearing the RIRB interrupt status ahead of
write pointer access ensures that this condition is avoided.
Signed-off-by: default avatarMohan Kumar <mkumard@nvidia.com>
Signed-off-by: default avatarViswanath L <viswanathl@nvidia.com>
Link: https://lore.kernel.org/r/1580983853-351-1-git-send-email-viswanathl@nvidia.comSigned-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent f2adbae0
......@@ -1110,16 +1110,23 @@ irqreturn_t azx_interrupt(int irq, void *dev_id)
if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update))
active = true;
/* clear rirb int */
status = azx_readb(chip, RIRBSTS);
if (status & RIRB_INT_MASK) {
/*
* Clearing the interrupt status here ensures that no
* interrupt gets masked after the RIRB wp is read in
* snd_hdac_bus_update_rirb. This avoids a possible
* race condition where codec response in RIRB may
* remain unserviced by IRQ, eventually falling back
* to polling mode in azx_rirb_get_response.
*/
azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
active = true;
if (status & RIRB_INT_RESPONSE) {
if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
udelay(80);
snd_hdac_bus_update_rirb(bus);
}
azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
}
} while (active && ++repeat < 10);
......
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