Commit 6d549ff5 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Kevin Hilman

ARM: dts: meson8b: add the DDR clock controller

Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
inputs for the audio clock muxes.
Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent c4ac5c37
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
* Author: Carlo Caione <carlo@endlessm.com> * Author: Carlo Caione <carlo@endlessm.com>
*/ */
#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8b-gpio.h> #include <dt-bindings/gpio/meson8b-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-reset.h> #include <dt-bindings/reset/amlogic,meson8b-reset.h>
...@@ -172,6 +173,14 @@ mmcbus: bus@c8000000 { ...@@ -172,6 +173,14 @@ mmcbus: bus@c8000000 {
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0xc8000000 0x8000>; ranges = <0x0 0xc8000000 0x8000>;
ddr_clkc: clock-controller@400 {
compatible = "amlogic,meson8b-ddr-clkc";
reg = <0x400 0x20>;
clocks = <&xtal>;
clock-names = "xtal";
#clock-cells = <1>;
};
dmcbus: bus@6000 { dmcbus: bus@6000 {
compatible = "simple-bus"; compatible = "simple-bus";
reg = <0x6000 0x400>; reg = <0x6000 0x400>;
...@@ -434,8 +443,8 @@ &gpio_intc { ...@@ -434,8 +443,8 @@ &gpio_intc {
&hhi { &hhi {
clkc: clock-controller { clkc: clock-controller {
compatible = "amlogic,meson8-clkc"; compatible = "amlogic,meson8-clkc";
clocks = <&xtal>; clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
clock-names = "xtal"; clock-names = "xtal", "ddr_pll";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
......
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