Commit 6d67ee9a authored by Shiju Jose's avatar Shiju Jose Committed by David S. Miller

net: hns3: Add enable and process common ecc errors

This patch adds enable and processing of ecc errors from
common HNS blocks, CMDQ(Command Queue),
IMP(Integrated Management Processor) and TQP(Task Queue Pair).
Signed-off-by: default avatarShiju Jose <shiju.jose@huawei.com>
Signed-off-by: default avatarSalil Mehta <salil.mehta@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 99714195
...@@ -209,6 +209,9 @@ enum hclge_opcode_type { ...@@ -209,6 +209,9 @@ enum hclge_opcode_type {
/* Led command */ /* Led command */
HCLGE_OPC_LED_STATUS_CFG = 0xB000, HCLGE_OPC_LED_STATUS_CFG = 0xB000,
/* Error INT commands */
HCLGE_COMMON_ECC_INT_CFG = 0x1505,
}; };
#define HCLGE_TQP_REG_OFFSET 0x80000 #define HCLGE_TQP_REG_OFFSET 0x80000
......
...@@ -11,6 +11,31 @@ ...@@ -11,6 +11,31 @@
#define HCLGE_RAS_REG_NFE_MASK 0xFF00 #define HCLGE_RAS_REG_NFE_MASK 0xFF00
#define HCLGE_RAS_REG_NFE_SHIFT 8 #define HCLGE_RAS_REG_NFE_SHIFT 8
#define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
#define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300
#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000
#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF0000
#define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x0100
#define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
#define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF
#define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
#define HCLGE_IMP_TCM_ECC_INT_MASK 0xFFFF
#define HCLGE_IMP_ITCM4_ECC_INT_MASK 0x3
#define HCLGE_CMDQ_ECC_INT_MASK 0xFFFF
#define HCLGE_CMDQ_ROC_ECC_INT_SHIFT 16
#define HCLGE_TQP_ECC_INT_MASK 0xFFF
#define HCLGE_TQP_ECC_INT_SHIFT 16
#define HCLGE_IMP_TCM_ECC_CLR_MASK 0xFFFF
#define HCLGE_IMP_ITCM4_ECC_CLR_MASK 0x3
#define HCLGE_CMDQ_NIC_ECC_CLR_MASK 0xFFFF
#define HCLGE_CMDQ_ROCEE_ECC_CLR_MASK 0xFFFF0000
#define HCLGE_TQP_IMP_ERR_CLR_MASK 0x0FFF0001
enum hclge_err_int_type { enum hclge_err_int_type {
HCLGE_ERR_INT_MSIX = 0, HCLGE_ERR_INT_MSIX = 0,
HCLGE_ERR_INT_RAS_CE = 1, HCLGE_ERR_INT_RAS_CE = 1,
...@@ -26,6 +51,11 @@ struct hclge_hw_blk { ...@@ -26,6 +51,11 @@ struct hclge_hw_blk {
enum hclge_err_int_type type); enum hclge_err_int_type type);
}; };
struct hclge_hw_error {
u32 int_msk;
const char *msg;
};
int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state); int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state);
pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev); pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev);
#endif #endif
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment