Commit 6e9057a8 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher

drm/amd/amdgpu: Tidy up SI IH code

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarEdward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 77d318a6
...@@ -57,7 +57,6 @@ static void si_ih_disable_interrupts(struct amdgpu_device *adev) ...@@ -57,7 +57,6 @@ static void si_ih_disable_interrupts(struct amdgpu_device *adev)
static int si_ih_irq_init(struct amdgpu_device *adev) static int si_ih_irq_init(struct amdgpu_device *adev)
{ {
int ret = 0;
int rb_bufsz; int rb_bufsz;
u32 interrupt_cntl, ih_cntl, ih_rb_cntl; u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
u64 wptr_off; u64 wptr_off;
...@@ -72,18 +71,15 @@ static int si_ih_irq_init(struct amdgpu_device *adev) ...@@ -72,18 +71,15 @@ static int si_ih_irq_init(struct amdgpu_device *adev)
WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8); WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE |
IH_WPTR_OVERFLOW_CLEAR | IH_WPTR_OVERFLOW_CLEAR |
(rb_bufsz << 1)); (rb_bufsz << 1) |
IH_WPTR_WRITEBACK_ENABLE;
ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
WREG32(IH_RB_CNTL, ih_rb_cntl); WREG32(IH_RB_CNTL, ih_rb_cntl);
WREG32(IH_RB_RPTR, 0); WREG32(IH_RB_RPTR, 0);
WREG32(IH_RB_WPTR, 0); WREG32(IH_RB_WPTR, 0);
...@@ -93,10 +89,9 @@ static int si_ih_irq_init(struct amdgpu_device *adev) ...@@ -93,10 +89,9 @@ static int si_ih_irq_init(struct amdgpu_device *adev)
WREG32(IH_CNTL, ih_cntl); WREG32(IH_CNTL, ih_cntl);
pci_set_master(adev->pdev); pci_set_master(adev->pdev);
si_ih_enable_interrupts(adev); si_ih_enable_interrupts(adev);
return ret; return 0;
} }
static void si_ih_irq_disable(struct amdgpu_device *adev) static void si_ih_irq_disable(struct amdgpu_device *adev)
...@@ -165,9 +160,7 @@ static int si_ih_sw_init(void *handle) ...@@ -165,9 +160,7 @@ static int si_ih_sw_init(void *handle)
if (r) if (r)
return r; return r;
r = amdgpu_irq_init(adev); return amdgpu_irq_init(adev);
return r;
} }
static int si_ih_sw_fini(void *handle) static int si_ih_sw_fini(void *handle)
...@@ -182,14 +175,9 @@ static int si_ih_sw_fini(void *handle) ...@@ -182,14 +175,9 @@ static int si_ih_sw_fini(void *handle)
static int si_ih_hw_init(void *handle) static int si_ih_hw_init(void *handle)
{ {
int r;
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = si_ih_irq_init(adev); return si_ih_irq_init(adev);
if (r)
return r;
return 0;
} }
static int si_ih_hw_fini(void *handle) static int si_ih_hw_fini(void *handle)
...@@ -229,12 +217,10 @@ static bool si_ih_is_idle(void *handle) ...@@ -229,12 +217,10 @@ static bool si_ih_is_idle(void *handle)
static int si_ih_wait_for_idle(void *handle) static int si_ih_wait_for_idle(void *handle)
{ {
unsigned i; unsigned i;
u32 tmp;
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) { for (i = 0; i < adev->usec_timeout; i++) {
tmp = RREG32(SRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK; if (si_ih_is_idle(handle))
if (!tmp)
return 0; return 0;
udelay(1); udelay(1);
} }
......
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