Commit 70807e99 authored by Sujith's avatar Sujith Committed by John W. Linville

ath9k_hw: update initialization values for AR9271

Update the register initialization values for AR9271.
This is based on our last review from our systems team.
Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarVasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent e21247cc
...@@ -603,9 +603,23 @@ static void ath9k_hw_init_mode_regs(struct ath_hw *ah) ...@@ -603,9 +603,23 @@ static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
ARRAY_SIZE(ar9271Modes_9271), 6); ARRAY_SIZE(ar9271Modes_9271), 6);
INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
ARRAY_SIZE(ar9271Common_9271), 2); ARRAY_SIZE(ar9271Common_9271), 2);
INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
ar9271Common_normal_cck_fir_coeff_9271,
ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
ar9271Common_japan_2484_cck_fir_coeff_9271,
ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
ar9271Modes_9271_1_0_only, ar9271Modes_9271_1_0_only,
ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6); ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
ar9271Modes_high_power_tx_gain_9271,
ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
ar9271Modes_normal_power_tx_gain_9271,
ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
return; return;
} }
...@@ -1266,26 +1280,6 @@ static void ath9k_hw_override_ini(struct ath_hw *ah, ...@@ -1266,26 +1280,6 @@ static void ath9k_hw_override_ini(struct ath_hw *ah,
{ {
u32 val; u32 val;
if (AR_SREV_9271(ah)) {
/*
* Enable spectral scan to solution for issues with stuck
* beacons on AR9271 1.0. The beacon stuck issue is not seeon on
* AR9271 1.1
*/
if (AR_SREV_9271_10(ah)) {
val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
AR_PHY_SPECTRAL_SCAN_ENABLE;
REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
}
else if (AR_SREV_9271_11(ah))
/*
* change AR_PHY_RF_CTL3 setting to fix MAC issue
* present on AR9271 1.1
*/
REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
return;
}
/* /*
* Set the RX_ABORT and RX_DIS and clear if off only after * Set the RX_ABORT and RX_DIS and clear if off only after
* RXE is set for MAC. This prevents frames with corrupted * RXE is set for MAC. This prevents frames with corrupted
...@@ -1294,8 +1288,10 @@ static void ath9k_hw_override_ini(struct ath_hw *ah, ...@@ -1294,8 +1288,10 @@ static void ath9k_hw_override_ini(struct ath_hw *ah,
REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
if (AR_SREV_9280_10_OR_LATER(ah)) { if (AR_SREV_9280_10_OR_LATER(ah)) {
val = REG_READ(ah, AR_PCU_MISC_MODE2) & val = REG_READ(ah, AR_PCU_MISC_MODE2);
(~AR_PCU_MISC_MODE2_HWWAR1);
if (!AR_SREV_9271(ah))
val &= ~AR_PCU_MISC_MODE2_HWWAR1;
if (AR_SREV_9287_10_OR_LATER(ah)) if (AR_SREV_9287_10_OR_LATER(ah))
val = val & (~AR_PCU_MISC_MODE2_HWWAR2); val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
...@@ -1439,7 +1435,10 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ...@@ -1439,7 +1435,10 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
return -EINVAL; return -EINVAL;
} }
/* Set correct baseband to analog shift setting to access analog chips */
REG_WRITE(ah, AR_PHY(0), 0x00000007); REG_WRITE(ah, AR_PHY(0), 0x00000007);
/* Write ADDAC shifts */
REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
ah->eep_ops->set_addac(ah, chan); ah->eep_ops->set_addac(ah, chan);
...@@ -1451,9 +1450,11 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ...@@ -1451,9 +1450,11 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
sizeof(u32) * ah->iniAddac.ia_rows * sizeof(u32) * ah->iniAddac.ia_rows *
ah->iniAddac.ia_columns; ah->iniAddac.ia_columns;
/* For AR5416 2.0/2.1 */
memcpy(ah->addac5416_21, memcpy(ah->addac5416_21,
ah->iniAddac.ia_array, addacSize); ah->iniAddac.ia_array, addacSize);
/* override CLKDRV value at [row, column] = [31, 1] */
(ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0; (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
temp.ia_array = ah->addac5416_21; temp.ia_array = ah->addac5416_21;
...@@ -1485,6 +1486,11 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ...@@ -1485,6 +1486,11 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
AR_SREV_9287_10_OR_LATER(ah)) AR_SREV_9287_10_OR_LATER(ah))
REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
if (AR_SREV_9271_10(ah))
REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
modesIndex, regWrites);
/* Write common array parameters */
for (i = 0; i < ah->iniCommon.ia_rows; i++) { for (i = 0; i < ah->iniCommon.ia_rows; i++) {
u32 reg = INI_RA(&ah->iniCommon, i, 0); u32 reg = INI_RA(&ah->iniCommon, i, 0);
u32 val = INI_RA(&ah->iniCommon, i, 1); u32 val = INI_RA(&ah->iniCommon, i, 1);
...@@ -1499,11 +1505,16 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ...@@ -1499,11 +1505,16 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
DO_DELAY(regWrites); DO_DELAY(regWrites);
} }
ath9k_hw_write_regs(ah, freqIndex, regWrites); if (AR_SREV_9271(ah)) {
if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
modesIndex, regWrites);
else
REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
modesIndex, regWrites);
}
if (AR_SREV_9271_10(ah)) ath9k_hw_write_regs(ah, freqIndex, regWrites);
REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
modesIndex, regWrites);
if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
...@@ -1517,6 +1528,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ...@@ -1517,6 +1528,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
if (OLC_FOR_AR9280_20_LATER) if (OLC_FOR_AR9280_20_LATER)
ath9k_olc_init(ah); ath9k_olc_init(ah);
/* Set TX power */
ah->eep_ops->set_txpower(ah, chan, ah->eep_ops->set_txpower(ah, chan,
ath9k_regd_get_ctl(regulatory, chan), ath9k_regd_get_ctl(regulatory, chan),
channel->max_antenna_gain * 2, channel->max_antenna_gain * 2,
...@@ -1524,6 +1536,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ...@@ -1524,6 +1536,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
min((u32) MAX_RATE_POWER, min((u32) MAX_RATE_POWER,
(u32) regulatory->power_limit)); (u32) regulatory->power_limit));
/* Write analog registers */
if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
"ar5416SetRfRegs failed\n"); "ar5416SetRfRegs failed\n");
......
...@@ -599,6 +599,11 @@ struct ath_hw { ...@@ -599,6 +599,11 @@ struct ath_hw {
struct ar5416IniArray iniModes_9271_1_0_only; struct ar5416IniArray iniModes_9271_1_0_only;
struct ar5416IniArray iniCckfirNormal; struct ar5416IniArray iniCckfirNormal;
struct ar5416IniArray iniCckfirJapan2484; struct ar5416IniArray iniCckfirJapan2484;
struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
struct ar5416IniArray iniModes_9271_ANI_reg;
struct ar5416IniArray iniModes_high_power_tx_gain_9271;
struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
u32 intr_gen_timer_trigger; u32 intr_gen_timer_trigger;
u32 intr_gen_timer_thresh; u32 intr_gen_timer_thresh;
......
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