Commit 70b894de authored by Evan Green's avatar Evan Green Committed by Kishon Vijay Abraham I

dt-bindings: phy: qcom-ufs: Add resets property

Add a resets property to the PHY that represents the PHY reset
register in the UFS controller itself. This better describes the
complete specification of the PHY, and allows the PHY to perform
its initialization in a single function, rather than relying on
back-channel sequencing of initialization through the PHY framework.
Signed-off-by: default avatarEvan Green <evgreen@chromium.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent 95cee0b4
...@@ -29,6 +29,7 @@ Optional properties: ...@@ -29,6 +29,7 @@ Optional properties:
- vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
- vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply - vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply
- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
- resets : specifies the PHY reset in the UFS controller
Example: Example:
...@@ -51,9 +52,11 @@ Example: ...@@ -51,9 +52,11 @@ Example:
<&clock_gcc clk_ufs_phy_ldo>, <&clock_gcc clk_ufs_phy_ldo>,
<&clock_gcc clk_gcc_ufs_tx_cfg_clk>, <&clock_gcc clk_gcc_ufs_tx_cfg_clk>,
<&clock_gcc clk_gcc_ufs_rx_cfg_clk>; <&clock_gcc clk_gcc_ufs_rx_cfg_clk>;
resets = <&ufshc 0>;
}; };
ufshc@fc598000 { ufshc: ufshc@fc598000 {
#reset-cells = <1>;
... ...
phys = <&ufsphy1>; phys = <&ufsphy1>;
phy-names = "ufsphy"; phy-names = "ufsphy";
......
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